Computer system including virtual memory or cache

US2016202907A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016202907-A1
Application numberUS-201514722606-A
CountryUS
Kind codeA1
Filing dateMay 27, 2015
Priority dateJan 14, 2015
Publication dateJul 14, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

According to one embodiment, a computer system includes a first memory unit, a second memory unit having a data transfer rate lower than that of the first memory unit and a controller. The controller controls transfer of unit data. The unit data includes an indicating portion indicating whether the unit data is to be retained in the second memory unit. When the unit data is transferred from the second memory unit to the first memory unit and the unit data is to be retained in the second memory unit, the controller sets a first state to the indicating portion of the respective unit data. When the unit data is transferred from the first memory unit to the second memory unit, the controller writes the respective unit data in which the indicating portion is set to the first state, to the second memory unit.

First claim

Opening claim text (preview).

What is claimed is: 1 . A computer system comprising: a first memory unit; a second memory unit having a data transfer rate lower than that of the first memory unit; and a controller configured to control transfer of unit data between the first memory unit and the second memory unit, the unit data comprising an indicating portion indicating whether the unit data is to be retained in the second memory unit, wherein when the unit data is transferred from the second memory unit to the first memory unit and the unit data is to be retained in the second memory unit, the controller sets a first state to the indicating portion of the respective unit data and, when the unit data is transferred from the first memory unit to the second memory unit, the controller writes the unit data in which the indicating portion is set to the first state, to the second memory unit. 2 . The system according to claim 1 , wherein the second memory unit comprises a memory of which data retained therein is destroyed when the data is read. 3 . The system according to claim 2 , wherein when the unit data is not to be retained in the second memory unit, the controller does not set the first state in the indicating portion corresponding to the unit data. 4 . The system according to claim 3 , wherein when the unit data is written after the unit data is transferred from the second memory unit to the first memory unit, the controller sets the first state to the indicating portion of the respective unit data. 5 . The system according to claim 4 , wherein the controller comprises a first management unit configured to manage a virtual memory space and a virtual address, and to manage transfer of the unit data between the first memory unit and the second memory unit. 6 . The system according to claim 5 , wherein the unit data is contained in a page. 7 . The system according to claim 4 , wherein the controller comprises a second management unit configured to write the unit data to the first memory unit based on a data write request and to read data corresponding to a read request from the second memory unit when data corresponding to the read request is absent in the first memory unit. 8 . The system according to claim 7 , wherein the unit data is data in units of lines of a cache. 9 . A server system comprising a plurality of computer systems of claim 1 mounted therein. 10 . A computer system comprising: a first memory unit; a second memory unit having a data transfer rate lower than that of the first memory unit; and a controller configured to control transfer of data of a page between the first memory unit and the second memory unit, the page comprising an indicating portion indicating whether the data of the page is to be retained in the second memory unit, wherein in a page-in where the data of the page is transferred from the second memory unit to the first memory unit, when the data of the page is not to be retained in the second memory unit, the controller does not set a first state to the indicating portion of the respective page, and when the data of the page is to be retained in the second memory unit, the controller sets the first state to the indicating portion of the respective page; and after the page-in, when the data of the page is written, the controller sets the first state to the indicating portion of the respective page, and in a page-out where transferring the data of the page from the first memory unit to the second memory unit, the controller writes the data of the page in which the indicating portion is set to the first state, to the second memory unit. 11 . The system according to claim 10 , wherein the second memory unit comprises a memory of which data retained therein is destroyed when the data is read. 12 . The system according to claim 11 , wherein the controller comprises a management unit configured to manage a virtual memory space and a virtual address, and to manage transfer of the data of the page between the first memory unit and the second memory unit. 13 . A server system comprising a plurality of computer systems of claim 10 mounted therein. 14 . A computer system comprising: a first memory unit; a second memory unit having a data transfer rate lower than that of the first memory unit; and a controller configured to control transfer of data of a line between the first memory unit and the second memory unit, the line comprising an indicating portion indicating whether the data of the line is to be retained in the second memory unit, wherein in a line-in where the data of the line is transferred from the second memory unit to the first memory unit, when the data of the line is not to be retained in the second memory unit, the controller does not set a first state to the indicating portion of the respective line, and when the data of the page is to be retained in the second memory unit, the controller sets the first state to the indicating portion of the respective line; and after the line-in, when the data of the line is written, the controller sets the first state to the indicating portion of the respective line, and in a page-out where the data of the line is transferred from the first memory unit to the second memory unit, the controller writes the data of the line in which the indicating portion is set to the first state, to the second memory unit. 15 . The system according to claim 14 , wherein the second memory unit comprises a memory of which data retained therein is destroyed when the data is read. 16 . The system according to claim 15 , wherein the controller comprises a management unit configured to write the data of the line in the first memory unit based on a data write request and read, when data corresponding to a read request is absent in the first memory unit, data corresponding to the read request from the second memory unit. 17 . A server system comprising a plurality of computer systems of claim 14 mounted therein.

Assignees

Inventors

Classifications

  • Migration mechanisms · CPC title

  • G06F3/061Primary

    Improving I/O performance · CPC title

  • Plurality of storage devices · CPC title

  • using page tables, e.g. page table structures · CPC title

  • for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title

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What does patent US2016202907A1 cover?
According to one embodiment, a computer system includes a first memory unit, a second memory unit having a data transfer rate lower than that of the first memory unit and a controller. The controller controls transfer of unit data. The unit data includes an indicating portion indicating whether the unit data is to be retained in the second memory unit. When the unit data is transferred from the…
Who is the assignee on this patent?
Toshiba Kk
What technology area does this patent fall under?
Primary CPC classification G06F3/061. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Jul 14 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).