Liquid crystal display and manufacturing method thereof

US2016202518A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016202518-A1
Application numberUS-201514932639-A
CountryUS
Kind codeA1
Filing dateNov 4, 2015
Priority dateJan 9, 2015
Publication dateJul 14, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A liquid crystal display is provided. The liquid crystal display includes: a substrate; a thin film transistor disposed on the substrate; a pixel electrode disposed on the thin film transistor; a roof layer facing the pixel electrode; and partition walls forming a plurality of microcavities between the pixel electrode and the roof layer, wherein the plurality of microcavities include liquid crystal molecules, and the partition walls include light blocking, materials.

First claim

Opening claim text (preview).

What is claimed is: 1 . A liquid crystal display comprising: a substrate; a thin film transistor disposed on the substrate; a pixel electrode disposed on the thin film transistor; a roof layer facing the pixel electrode; and partition walls forming a plurality of microcavities between the pixel electrode and the roof layer, wherein the plurality of microcavities comprise liquid crystal molecules, and the partition walls include light blocking materials. 2 . The liquid crystal display of claim 1 , further comprising: an inlet of the microcavity disposed between the partition wall and the roof layer. 3 . The liquid crystal display of claim 2 , wherein: the partition walls include horizontal partition walls that are in parallel with gate lines connected to the thin film transistor and vertical partition walls that are in parallel with data lines connected to the thin film transistor. 4 . The liquid crystal display of claim 3 , wherein: the inlet is formed by opening a portion of the roof layer adjacent to the horizontal partition wall. 5 . The liquid crystal display of claim 4 , wherein: the inlet has a shape in which the inlet is lengthily extended along the horizontal partition wall. 6 . The liquid crystal display of claim 5 , wherein: the inlet is disposed adjacently to a portion at which the horizontal partition wall and the vertical partition wall meet each other. 7 . The liquid crystal display of claim 3 , wherein: the inlet includes a plurality of regions having a shape in which the regions are lengthily extended along the horizontal partition wall or the vertical partition wall at a portion corresponding to one of the plurality of microcavities. 8 . The liquid crystal display of claim 3 , wherein: when the respective pixels enclosing an intersection region of the gate line and the data line are a first pixel, a second pixel, a third pixel, and a fourth pixel, the inlets are disposed adjacently to the intersection region in the respective pixels. 9 . The liquid crystal display of claim 4 , further comprising: a common electrode disposed below the roof layer and facing the pixel electrode based on the plurality of microcavities. 10 . The liquid crystal display of claim 9 , wherein: the inlet simultaneously penetrates through the roof layer and the common electrode. 11 . The liquid crystal display of claim 3 , wherein: a partition wall of the partition walls forming one microcavity of the plurality of microcavities is isolated from a partition wall of the partition walls of another microcavity of the plurality of microcavities neighboring to the one microcavity in a direction in which the gate lines are extended. 12 . The liquid crystal display of claim 3 , wherein: the horizontal partition wall comprises a groove structure. 13 . The liquid crystal display of claim 3 , wherein: the inlet is disposed in a portion overlapped with the partition wall. 14 . The liquid crystal display of claim 13 , wherein: the inlet is disposed between the roof layer and the horizontal partition wall. 15 . The liquid crystal display of claim 3 , wherein: the horizontal partition wall covers the thin film transistor. 16 . The liquid crystal display of claim 2 , further comprising: a capping layer disposed on the roof layer, wherein the capping layer covers the inlet. 17 . A manufacturing method of a liquid crystal display, comprising: forming a thin film transistor on a substrate; forming a pixel electrode on the thin film transistor; forming a light blocking material layer on the pixel electrode; exposing a preliminary partition wall region of the light blocking material layer; forming a roof material layer on the light blocking material layer; patterning the roof material layer by a photo process to form a roof layer; and developing the exposed light blocking material layer to form partition walls, wherein the partition walls form a plurality of microcavities between the pixel electrode and the roof layer. 18 . The manufacturing method of a liquid crystal display of claim 17 , further comprising: forming inlets of the plurality of microcavities between the partition walls and the roof layer. 19 . The manufacturing method of a liquid crystal display of claim 18 , wherein: the light blocking material layer has negative photo characteristics. 20 . The manufacturing method of a liquid crystal display of claim 19 , wherein: exposure wavelengths in the exposing of the preliminary partition wall region and in the patterning of the roof material layer by the photo process to form the roof layer are different from each other.

Assignees

Inventors

Classifications

  • of multiple TFTs · CPC title

  • Light shielding layers, e.g. black matrix (G02F1/136209 takes precedence) · CPC title

  • G02F1/1341Primary

    Filling or closing of cells · CPC title

  • in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

  • Electricity · mapped topic

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What does patent US2016202518A1 cover?
A liquid crystal display is provided. The liquid crystal display includes: a substrate; a thin film transistor disposed on the substrate; a pixel electrode disposed on the thin film transistor; a roof layer facing the pixel electrode; and partition walls forming a plurality of microcavities between the pixel electrode and the roof layer, wherein the plurality of microcavities include liquid cry…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G02F1/1341. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Jul 14 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).