Power semiconductor devices having superjunction structures with implanted sidewalls and methods of fabricating such devices

Patent metadata

Field	Value
Publication number	US-2016197201-A1
Application number	US-201514588527-A
Country	US
Kind code	A1
Filing date	Jan 2, 2015
Priority date	Jan 2, 2015
Publication date	Jul 7, 2016
Grant date	—

Abstract

A semiconductor device has a drift region having an upper surface and a lower surface. A first contact is on the upper surface of the drift region and a second contact is on the lower surface of the drift region. The drift region includes a first semiconductor pillar that has a tapered sidewall and that is doped with first conductivity type impurities and a second semiconductor pillar on the tapered sidewall of the first semiconductor pillar, the second semiconductor pillar doped with second conductivity type impurities that have an opposite conductivity from the first conductivity type impurities.

First claim

1 . A semiconductor device, comprising:
a drift region having an upper portion and a lower portion; a first contact on the upper portion of the drift region; and a second contact on the lower portion of the drift region, wherein the drift region includes:
a first semiconductor pillar that has a tapered sidewall and that is doped with first conductivity type impurities; and
a second semiconductor pillar on the tapered sidewall of the first semiconductor pillar, the second semiconductor pillar doped with second conductivity type impurities that have an opposite conductivity from the first conductivity type impurities.

2 . The semiconductor device of claim 1 , further comprising a third semiconductor pillar on the second semiconductor pillar, the third semiconductor pillar doped with first conductivity type impurities.

3 . The semiconductor device of claim 2 , wherein the third semiconductor pillar has a doping concentration of the first conductivity type impurities that is at least fifty times lower than the doping concentration of the first conductivity type impurities in the first semiconductor pillar.

4 . The semiconductor device of claim 2 , wherein the first through third semiconductor pillars are charge balanced such that the charges in the first and third semiconductor pillars approximately equal the charges in the second semiconductor pillar.

5 . The semiconductor device of claim 1 , wherein the drift region is on a 4H silicon carbide substrate, and wherein the first semiconductor pillar and the second semiconductor pillar each comprise silicon carbide pillars.

6 - 8 . (canceled)

9 . The semiconductor device of claim 2 , wherein the third semiconductor pillar surrounds the first semiconductor pillar, and the second semiconductor pillar is between the first semiconductor pillar and the third semiconductor pillar.

10 . The semiconductor device of claim 1 , further comprising a 4H silicon carbide substrate, wherein an active region of the semiconductor device extends along the <10-10> crystallographic direction of the substrate.

11 . (canceled)

12 . The semiconductor device of claim 2 , further comprising a substrate that is between the lower portion of the drift region and the second contact, wherein an axis that is normal to an upper surface of the substrate that penetrates the tapered sidewall of the first semiconductor pillar also penetrates an upper portion of the third semiconductor pillar.

13 . The semiconductor device of claim 12 , wherein the third semiconductor pillar has a doping concentration of the first conductivity type impurities that is at least fifty times lower than the doping concentration of the first conductivity type impurities in the first semiconductor pillar.

14 - 15 . (canceled)

16 . The semiconductor device of claim 2 , wherein a width of the first semiconductor pillar is at least three times a width of the second semiconductor pillar.

17 . A semiconductor device, comprising:
a drift region having an upper surface and a lower surface; a first contact on the upper surface of the drift region; and a second contact on the lower surface of the drift region, wherein the drift region includes:
a first semiconductor pillar that is doped with first conductivity type impurities; and
a second semiconductor pillar that is doped with first conductivity type impurities on the first semiconductor pillar,
wherein the second semiconductor pillar has a doping concentration of the first conductivity type impurities that is at least fifty times lower than the doping concentration of the first conductivity type impurities in the first semiconductor pillar.

18 . The semiconductor device of claim 17 , further comprising a third semiconductor pillar between the first semiconductor pillar and the second semiconductor pillar, the third semiconductor pillar doped with second conductivity type impurities that have an opposite conductivity from the first conductivity type impurities, wherein the first through third semiconductor pillars form a superjunction structure.

19 . The semiconductor device of claim 18 , wherein the first through third semiconductor pillars are on an upper surface of a substrate, and wherein the third semiconductor pillar is tapered so that it forms an oblique angle with the upper surface of the substrate.

20 . (canceled)

21 . The semiconductor device of claim 18 , wherein the first through third semiconductor pillars are charge balanced such that the charges in the first and second semiconductor pillars approximately equal the charges in the third semiconductor pillar.

22 . (canceled)

23 . The semiconductor device of claim 18 , further comprising an edge termination, wherein the third semiconductor pillar is between the first semiconductor pillar and the edge termination.

24 - 26 . (canceled)

27 . The semiconductor device of claim 19 , wherein an axis that is normal to the upper surface of the substrate penetrates both the tapered sidewall of the first semiconductor pillar and an upper portion of the second semiconductor pillar.

28 - 29 . (canceled)

30 . The semiconductor device of claim 19 , wherein the oblique angle is less than eighty degrees or greater than 100 degrees.

31 - 40 . (canceled)

41 . A semiconductor device, comprising:
a drift region having an upper portion and a lower portion; a first contact on the upper portion of the drift region; and a second contact on the lower portion of the drift region, wherein the drift region includes:
a first semiconductor pillar that has a tapered sidewall;
a second semiconductor pillar on the tapered sidewall of the first semiconductor pillar; and
a third semiconductor pillar on the second semiconductor pillar.

42 . The semiconductor device of claim 41 , wherein the first semiconductor pillar is doped with first conductivity type impurities,. and the second semiconductor pillar is doped with second conductivity type impurities that have an opposite conductivity from the first conductivity type impurities, and the third semiconductor pillar is doped with first conductivity type impurities.

43 . (canceled)

44 . The semiconductor device of claim 42 , wherein the third semiconductor pillar has a doping concentration of the first conductivity type impurities that is at least fifty times lower than the doping concentration of the first conductivity type impurities in the first semiconductor pillar.

45 - 48 . (canceled)

Assignees

• Cree Inc

Inventors

• Van Brunt Edward Robert
• Pala Vipindas
• Cheng Lin
• Lichtenwalner Daniel J

Classifications

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P30/2042

  into crystalline silicon carbide · CPC title

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10D62/405

  Orientations of crystalline planes · CPC title

• H10D62/126

  Top-view geometrical layouts of the regions or the junctions · CPC title