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Semiconductor device and manufacturing method of the same
US2016197174A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016197174-A1 |
| Application number | US-201414911680-A |
| Country | US |
| Kind code | A1 |
| Filing date | Sep 8, 2014 |
| Priority date | Sep 30, 2013 |
| Publication date | Jul 7, 2016 |
| Grant date | — |
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Abstract
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A semiconductor device includes a first compound semiconductor layer, a second compound semiconductor layer having a larger band gap than that of the first compound semiconductor layer, p-type third compound semiconductor layer disposed above a portion of the second compound semiconductor layer, a p-type fourth compound semiconductor layer disposed above the third compound semiconductor layer and having a higher resistance than that of the third compound semiconductor layer, and a gate electrode disposed above the fourth compound semiconductor layer.
First claim
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1 . A semiconductor device comprising: a first compound semiconductor layer; a second compound semiconductor layer disposed on the first compound semiconductor layer and having a larger band gap than that of the first compound semiconductor layer; a p-type third compound semiconductor layer disposed above a portion of the second compound semiconductor layer; a p-type fourth compound semiconductor layer disposed above the third compound semiconductor layer and has a higher resistance than that of the third compound semiconductor layer; and a gate electrode disposed above the fourth compound semiconductor layer. 2 . The semiconductor device according to claim 1 , wherein a concentration of p-type impurities contained in the fourth compound semiconductor layer is lower than a concentration of p-type impurities contained in the third compound semiconductor layer. 3 . The semiconductor device according to claim 1 , wherein the fourth compound semiconductor layer has a lower crystallinity than that of the third compound semiconductor layer. 4 . The semiconductor device according to claim 1 , wherein the first compound semiconductor layer, the second compound semiconductor layer, the third compound semiconductor layer and the fourth compound semiconductor layer comprise nitride semiconductor. 5 . A manufacturing method of a semiconductor device, the method comprising: a first step of forming a second compound semiconductor layer on a first compound semiconductor layer, the second compound semiconductor layer having a larger band gap than that of the first compound semiconductor layer; a second step of forming a p-type third compound semiconductor layer above a portion of the second compound semiconductor layer; a third step of forming a p-type fourth compound semiconductor layer above the third compound semiconductor layer, the fourth compound semiconductor layer having a higher resistance than that of the third compound semiconductor layer; and a fourth step of forming a gate electrode above the fourth compound semiconductor layer. 6 . The manufacturing method according to claim 5 , wherein the third step comprises crystal-growing the fourth compound semiconductor layer above the third compound semiconductor layer, the fourth compound semiconductor layer having a concentration of p-type impurities lower than a concentration of p-type impurities in the third compound semiconductor layer. 7 . The manufacturing method according to claim 5 , wherein the second step and the third step comprise: forming a p-type compound semiconductor layer above the portion of the second compound semiconductor layer; and exposing a surface of the p-type compound semiconductor layer to plasma, wherein a portion of the p-type compound semiconductor layer that was not exposed to the plasma serves as the third compound semiconductor layer, and a portion of the p-type compound semiconductor layer that was exposed to the plasma serves as the fourth compound semiconductor layer.
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Classifications
P-type · CPC title
Nitrides · CPC title
consisting of two layers · CPC title
Nitrides · CPC title
being crystalline insulating materials · CPC title
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- What does patent US2016197174A1 cover?
- A semiconductor device includes a first compound semiconductor layer, a second compound semiconductor layer having a larger band gap than that of the first compound semiconductor layer, p-type third compound semiconductor layer disposed above a portion of the second compound semiconductor layer, a p-type fourth compound semiconductor layer disposed above the third compound semiconductor layer a…
- Who is the assignee on this patent?
- Toyota Motor Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D30/015. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Jul 07 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).