Display apparatus
US-2024414942-A1 · Dec 12, 2024 · US
US2016197130A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016197130-A1 |
| Application number | US-201514866288-A |
| Country | US |
| Kind code | A1 |
| Filing date | Sep 25, 2015 |
| Priority date | Jan 5, 2015 |
| Publication date | Jul 7, 2016 |
| Grant date | — |
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A display device including: a first conductive pattern group including: a scan line and a gate electrode spaced from the scan line, a driving semiconductor pattern below the first conductive pattern group and including: a channel region overlapping the gate electrode; a source region; and a drain region, the channel region between the source region and the drain region; a second conductive pattern group on the first conductive pattern group and including: a data line crossing the scan line; a drain electrode coupled to the drain region; a pixel electrode extending from the drain electrode; a first coupling pattern coupled to the gate electrode; and a driving voltage line coupled to the source region; and a capacitor coupled to the first coupling pattern and the driving voltage line and overlapping the pixel electrode.
Opening claim text (preview).
What is claimed is: 1 . A display device, comprising: a first conductive pattern group comprising a scan line and a gate electrode spaced from the scan line; a driving semiconductor pattern below the first conductive pattern group and comprising: a channel region overlapping the gate electrode; a source region; and a drain region, the channel region between the source region and the drain region; a second conductive pattern group on the first conductive pattern group and comprising: a data line crossing the scan line; a drain electrode coupled to the drain region; a pixel electrode extending from the drain electrode; a first coupling pattern coupled to the gate electrode; and a driving voltage line coupled to the source region; and a capacitor coupled to the first coupling pattern and the driving voltage line and overlapping the pixel electrode. 2 . The display device as claimed in claim 1 , wherein the capacitor comprises: a first capacitor electrode spaced from the driving semiconductor pattern below the first conductive pattern group and overlapping the pixel electrode; a first gate insulating layer on the driving semiconductor pattern and the first capacitor electrode below the first conductive pattern group; a second gate insulating layer on the first gate insulating layer and the first conductive pattern group below the second conductive pattern group; and a second capacitor electrode on the first capacitor electrode with the first and second gate insulating layers therebetween. 3 . The display device as claimed in claim 2 , further comprising: a protruding portion extending from the first capacitor electrode and overlapping the driving voltage line; a protective layer on the second capacitor electrode and below the second conductive pattern group; and a contact portion extending from the driving voltage line towards the protruding portion and passing through the protective layer and the first and second gate insulating layers, the contact portion contacting the protruding portion. 4 . The display device as claimed in claim 2 , further comprising: a protective layer on the second capacitor electrode and below the second conductive pattern group; and a contact portion extending from the first coupling pattern towards the second capacitor electrode and passing through the protective layer, the contact portion contacting the second capacitor electrode. 5 . The display device as claimed in claim 2 , wherein the first capacitor electrode comprises a semiconductor pattern. 6 . The display device as claimed in claim 2 , wherein the first capacitor electrode comprises impurities of a same type as that of the source region and the drain region. 7 . The display device as claimed in claim 2 , wherein the second capacitor electrode comprises a metal layer. 8 . The display device as claimed in claim 1 , wherein the capacitor comprises: a first capacitor electrode spaced from the driving semiconductor pattern below the first conductive pattern group and overlapping the pixel electrode; a first gate insulating layer on the driving semiconductor pattern and the first capacitor electrode below the first conductive pattern group; and a second capacitor electrode on the first capacitor electrode with the first gate insulating layer therebetween and spaced from the scan line and the gate electrode, wherein the first conductive pattern group further comprises the second capacitor electrode. 9 . The display device as claimed in claim 8 , further comprising: a protruding portion extending from the first capacitor electrode and overlapping the driving voltage line; a second gate insulating layer on the first conductive pattern group and below the second conductive pattern group; a protective layer on the second gate insulating layer below the second conductive pattern group; and a contact portion extending from the driving voltage line towards the protruding portion and passing through the protective layer and the first and second gate insulating layers, the contact portion contacting the protruding portion. 10 . The display device as claimed in claim 8 , further comprising: a second gate insulating layer on the first conductive pattern group and below the second conductive pattern group; a protective layer on the second gate insulating layer below the second conductive pattern group; and a contact portion extending from the first coupling pattern towards the second capacitor electrode and passing through the protective layer and the second gate insulating layer, the contact portion contacting the second capacitor electrode. 11 . The display device as claimed in claim 8 , wherein the first capacitor electrode comprises a semiconductor pattern. 12 . The display device as claimed in claim 8 , wherein the first capacitor electrode comprises an undoped area overlapping the second capacitor electrode and a doped area offset from the second capacitor electrode. 13 . The display device as claimed in claim 12 , wherein the doped area comprises impurities of a same type as that of the source region and the drain region. 14 . The display device as claimed in claim 1 , wherein the capacitor comprises: a first capacitor electrode overlapping the pixel electrode on a first gate insulating layer, on the driving semiconductor pattern, and spaced from the scan line and the gate electrode; a second gate insulating layer on the first conductive pattern group and on the first gate insulating layer; and a second capacitor electrode on the first capacitor electrode with the second gate insulating layer therebetween and below the second conductive pattern group, wherein the first conductive pattern group further comprises the first capacitor electrode. 15 . The display device as claimed in claim 14 , further comprising: a protective layer on the second capacitor electrode below the second conductive pattern group and on the second gate insulating layer; and a contact portion extending from the first coupling pattern towards the first capacitor electrode and passing through the protective layer and the second gate insulating layer, the contact portion contacting the first capacitor electrode. 16 . The display device as claimed in claim 14 , further comprising: a protruding portion extending from the second capacitor electrode and overlapping the driving voltage line; a protective layer on the second capacitor electrode, on the protruding portion and below the second conductive pattern group; and a contact portion extending from the driving voltage line towards the protruding portion and passing through the protective layer, the contact portion contacting the protruding portion. 17 . The display device as claimed in claim 14 , wherein the second capacitor electrode comprises a metal layer. 18 . The display device as claimed in claim 1 , wherein the capacitor comprises: a first capacitor lower electrode overlapping the pixel electrode and spaced from the driving semiconductor pattern; a first gate insulating layer on the driving semiconductor pattern and the first capacitor lower electrode; a second capacitor electrode overlapping the first capacitor lower electrode on the first gate insulating layer and spaced from the scan line and the gate electrode; a second gate insulating layer on the first conductive pattern group and on the first gate insulating layer; and a first capacitor upper electrode coupled to the first capacitor lower electrode and overlapping the second capacitor electrode,
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