Vertical memory devices and related methods of manufacture

Patent metadata

Field	Value
Publication number	US-2016197092-A1
Application number	US-201514590081-A
Country	US
Kind code	A1
Filing date	Jan 6, 2015
Priority date	Jan 6, 2015
Publication date	Jul 7, 2016
Grant date	—

Abstract

A vertical semiconductor memory device having conducting and charge-trapping columns separated by columns of holes is disclosed. The columns are formed in layers of alternating conducting and insulating material with the conducting/charge-trapping columns and columns of holes separating layers of conducting material into disjoint strips. The conducting columns and separated layers of conducting material form wordlines and bitlines in the device.

First claim

What is claimed is:

1 . A three-dimensional semiconductor memory device comprising:
a plurality of alternating layers of conducting material and insulating material overlying a substrate; a plurality of first holes in the alternating layers disposed in first rows, wherein:
the first holes are lined with information storage film; and
the lined first holes are filled with conducting material that forms conducting columns;
a plurality of isolation holes disposed in the alternating layers between and linking adjacent first holes in the first rows; and a plurality of column connectors that connect conducting columns in second rows, wherein the second rows cross the first rows at an angle.

2 . The three-dimensional semiconductor memory device as set forth in claim 1 , wherein:
the first rows are parallel; and the angle not a right angle.

3 . The three-dimensional semiconductor memory device as set forth in claim 2 , wherein a memory cell in the semiconductor memory device having an angle of about 60° is about 86.6% of the size of a memory cell in the semiconductor device having an angle of about 90°.

4 . The three-dimensional semiconductor memory device as set forth in claim 1 , wherein the conducting columns comprise wordlines defining a vertical gate memory device.

5 . The three-dimensional semiconductor memory device as set forth in claim 4 , wherein a form of the conducting columns is modified to create a finFET-like vertical gate memory device.

6 . The three-dimensional semiconductor memory device as set forth in claim 1 , wherein the conducting columns comprise bitlines defining a vertical channel memory device.

7 . The three-dimensional semiconductor memory device as set forth in claim 1 , wherein:
the layers of conducting material comprise one or more of polycrystalline silicon, doped polycrystalline silicon, single-crystalline silicon, metal silicide, titanium, titanium nitride, tungsten, tungsten nitride, tallium, tallium nitride, and platinum; and the layers of insulating material comprise one or more of SiO 2 , doped oxide, SiOC, silicon nitride, SiON, SiOF, or metal oxide.

8 . The three-dimensional semiconductor memory device as set forth in claim 1 , wherein the first plurality of holes have a circular cross-section.

9 . The three-dimensional semiconductor memory device as set forth in claim 1 , wherein the first plurality of holes have a cross-section that is not circular.

10 . A method, comprising:
providing a vertical semiconductor stack comprising alternately-spaced insulating and conducting layers formed above a base layer; forming a plurality of first holes in the alternating layers, the first holes being disposed in an arrangement based on a regular pattern; lining the first holes with information storage films; filling-in the lined first holes with conducting material to form conducting columns; forming an overlying conducting layer connected to the conducting columns; disposing isolation holes between adjacent first holes in first rows, the isolation holes linking with the first holes; removing portions of the overlying conducting layer to form column connectors connecting conducting columns in second rows that form an angle with the first rows.

11 . The method as set forth in claim 10 , wherein:
the forming of the first holes comprises disposing the first holes in a regular pattern based upon corners of a square; and the removing comprises forming column connectors connecting columns in second rows that form an angle of about 90° with the first rows.

12 . The method as set forth in claim 10 , wherein:
the forming of the first holes comprises disposing the first holes in a regular pattern based upon vertices of an equilateral triangle; and the removing comprises forming column connectors connecting columns in second rows that form an angle of about 60° with the first rows.

13 . The method as set forth in claim 10 , wherein:
the lining comprises forming liners in the first holes, the liners comprising multilayer dielectric charge-trapping structures; and the filling-in comprises disposing conducting material comprising one or more of polycrystalline silicon, doped polycrystalline silicon, single-crystalline silicon, metal silicide, titanium, titanium nitride, tungsten, tungsten nitride, tallium, tallium nitride, and platinum into the lined first holes, thereby filling the holes.

14 . A semiconductor memory device comprising:
parallel rows of stacks of alternating layers of conducting material and insulating material; parallel rows of columns connected with and separating the parallel rows of stacks, wherein:
the rows of columns comprise alternating first columns and second columns linked together;
the first columns comprise outer layers of information storage films and inner cores of conducting material that forms conducting columns separated by the second columns; and
rows of conducting material that overlie the conducting columns and are connected to conducting columns in rows that form an angle with the parallel rows.

15 . The semiconductor memory device as set forth in claim 14 , wherein:
the parallel rows of stacks of conducting material form bitlines; the conducting columns form wordlines; and the semiconductor memory device is a vertical gate memory device.

16 . The semiconductor memory device as set forth in claim 14 , wherein:
the parallel rows of stacks of conducting material form wordlines; the conducting columns form bitlines; and the semiconductor memory device is a vertical channel memory device.

17 . The semiconductor memory device as set forth in claim 14 , wherein:
the conducting material comprises one or more of polycrystalline silicon, doped polycrystalline silicon, single-crystalline silicon, metal silicide, titanium, titanium nitride, tungsten, tungsten nitride, tallium, tallium nitride, and platinum; and the insulating material comprises one or more of SiO 2 , doped oxide, SiOC, silicon nitride, SiON, SiOF, and metal oxide.

18 . The semiconductor memory device as set forth in claim 14 , wherein the angle is not a right angle.

19 . The semiconductor memory device as set forth in claim 14 , wherein the information storage films comprise a tunnel layer, a charge trapping layer, and a blocking layer.

20 . The semiconductor memory device as set forth in claim 19 , wherein:
the tunnel layer comprises one or more of an oxide of silicon and a metal oxide; the blocking layer comprises one or more of an oxide of silicon and a metal oxide; and the charge trapping layer comprises one or more of silicon nitride and a metal oxide.

Assignees

• Macronix Int Co Ltd

Inventors

• Hong Shih-Ping

Classifications

• H10D62/122

  oriented at angles to substrates, e.g. perpendicular to substrates · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H01L23/528

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L29/0653

  Electricity · mapped topic