Semiconductor structure and fabrication method thereof, and static random access memory cell

Patent metadata

Field	Value
Publication number	US-2016197085-A1
Application number	US-201614986979-A
Country	US
Kind code	A1
Filing date	Jan 4, 2016
Priority date	Jan 6, 2015
Publication date	Jul 7, 2016
Grant date	—

Abstract

A method for forming a semiconductor having a plurality of FinFETs. The method includes providing a semiconductor substrate having a surface; and forming a plurality of first fins and a plurality of second fins on the surface of the semiconductor substrate. Further, the method also includes forming a mask layer on top surfaces of the plurality of first fins and the plurality of second fins; and forming an insulation material layer covering side surfaces of the first fins, the second fins and the mask layer. Further, the method includes removing a portion of the mask layer on the first fins; and forming a continuous first gate structure covering side and top surfaces of a plurality of first fins and a discontinuous second gate structure covering only the side surfaces of the second fins and the side surfaces of the mask layer.

First claim

What is claimed is:

1 . A method for fabricating a semiconductor structure having a plurality of FinFETs, comprising:
providing a semiconductor substrate having a surface; forming a plurality of first fins and a plurality of second fins on the surface of the semiconductor substrate; forming a mask layer on top surfaces of the plurality of first fins and the plurality of second fins; forming an insulation material layer covering side surfaces of the first fins, the second fins and the mask layer; removing a portion of the mask layer on the first fins; and forming a continuous first gate structure covering side and top surfaces of a plurality of first fins and a discontinuous second gate structure covering only the side surfaces of the second fins and the side surfaces of the mask layer.

2 . The method according to claim 1 , wherein:
a thickness of the mask layer is in a range of approximately 500 Ř600 Å.

3 . The method according to claim 1 , wherein removing the portion of the mask layer on the top surfaces of the first fins further comprises:
forming a patterned mask layer exposing the portion of the mask layer on the first fins on the insulation material layer and the mask layer; and removing the portion of mask layer on the top surfaces of the first fins to expose the top surfaces of the first fins.

4 . The method according to claim 1 , after removing the portion of the first mask layer on the top surfaces of the first fins, further comprising:
performing an etch-back process on the insulation material layer to form an insulation layer, of which a top surface is lower than the top surfaces of the first fins and the second fins.

5 . The method according to claim 4 , wherein forming the continuous first gate structure and the discontinuous second gate structure further comprises:
forming a first dummy gate structure covering the side and top surfaces of the plurality of first fins and a second dummy gate structure covering the side surfaces of the plurality of second fins and the mask layer on the insulation layer; forming a first dielectric layer covering side surfaces of the first dummy gate structure and the second dummy gate structure on the insulation layer; removing the first dummy gate structure and the second dummy gate structure to from a first trench and a second trench, respectively; and forming the first gate structure in the first trench and the second gate structure in the second trench.

6 . The method according to claim 5 , wherein:
the first dummy gate structure includes a first dummy gate dielectric layer and a first dummy gate layer formed on the first dummy gate dielectric layer; and the second dummy gate structure includes a second dummy gate dielectric layer and a second dummy gate layer formed on the second dummy gate dielectric layer.

7 . The method according to claim 5 , before forming the first dielectric layer, further comprising:
forming first source and drain regions in the first fins at both sides of the first dummy gate structure; and forming second source and drain regions in the second fins at both sides of the second dummy gate structure.

8 . The method according to claim 5 , further comprising:
forming first metal contact vias on the first source and drain regions; and forming second metal contact vias on the second source and drain regions.

9 . The method according to claim 8 , wherein forming the first metal contact vias and the second metal contact vias further comprises:
forming a second dielectric layer on the first dielectric layer, the first gate structure and the second gate structure; etching the second dielectric layer to form first through-holes to expose the first gate structure and the second gate structure; etching the second dielectric layer and the first dielectric layer to form second through-holes to expose the first source and drains and the second source and drain regions; and filling the first through-holes and the second through-holes with a metal material.

10 . The method according to claim 8 , wherein:
the first metal contact via on a portion of the second gate structure on one side surface of the second fin is used to apply a back-bias to adjust a threshold voltage of a FinFET formed by the second gate structure and the second fin.

11 . A semiconductor structure having a plurality, comprising:
a semiconductor substrate having a surface; a plurality of first fins and a plurality of second fins; a mask layer formed on top surfaces of the second fins; a continuous first gate structure covering side and top surfaces of a plurality of first fins; and a discontinuous second gate structure covering only side surfaces of the second fins and the side surfaces of the mask layer, wherein one portion the discontinuous second gate structure on one side surface of the second fins is used as a back-gate of a FinFET having the second gate structure and the second fin for adjusting a threshold voltage of the FinFET.

12 . The semiconductor structure according to claim 11 , further comprising:
first source and drain regions formed in the first fins at both sides of the first gate structure; second source and drain regions formed in the second fins at both sides of the second gate structure; an insulation layer covering portions of side surfaces of the first fins and the second fins formed over the surface of the semiconductor substrate, of which a top surface is lower than top surfaces of the first fins and the second fins; a first dielectric layer covering portion of side surfaces of the first fins, the second fins, the first gate structure, the second gate structure and the mask layer formed on the insulation layer, of which a top surface levels with the top surfaces the mask layer, the first gate structure and the second gate structure; a second dielectric layer formed on the first dielectric layer; first metal contact vias penetrating through the first dielectric layer and electrically connecting with the first gate structure and the second gate structure; and second metal contact vias penetrating through the second dielectric layer and the first dielectric layer and electrically connecting with the first source and drain regions and the second source and drain regions.

13 . The semiconductor structure according to claim 12 , wherein:
one of the first metal contact via is connected to the back-gate for providing a back-bias to adjust the threshold voltage of the FinFET.

14 . The semiconductor structure according to claim 11 , wherein:
a thickness of the mask layer is in a range of 500 Ř600 Å.

15 . The semiconductor structure according to claim 14 , wherein:
the mask layer is made of silicon nitride.

16 . A static random access memory (SRAM) cell, comprising:
a pass-gate transistor having a fin, a mask layer covering a portion of a top surface of the fin, and a back-gate and a gate covering portions of two side surfaces of the fin, respectively; a pull-up transistor, of which a source is electrically connected with the back-gate of the pass-gate transistor for providing a back bias to adjust a threshold voltage of the pass-gate transistor; and a pull-down transistor.

17 . The static random access memory (SRAM) cell according to claim 16 , wherein:
a gate of the pull-up transistors and a gate of the pull-down transistor are electrically connected.

18 . The static random access memory (SRAM) cell according to claim 16 , wherein:
the pull-up transistor and the pull-down transistor are FinFET transistors

Assignees

• Semiconductor Mfg Int Shanghai

Inventors

• Ju Jianhua
• Yu Shaofeng

Classifications

• H10P95/80

  Electrical treatments, e.g. for electroforming · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/0179

  the gate conductors having different shapes or dimensions · CPC title