Resistive random-access memory cells

Patent metadata

Field	Value
Publication number	US-2016196874-A1
Application number	US-201615070716-A
Country	US
Kind code	A1
Filing date	Mar 15, 2016
Priority date	Jun 28, 2013
Publication date	Jul 7, 2016
Grant date	—

Abstract

Improved random-access memory cells, complementary cells, and memory devices. The present invention provides a RRAM cell for storing information in a plurality of programmable cell states. The RRAM cell includes: an electrically-insulating matrix located between a first electrode and a second electrode such that an electrically-conductive path, extending in a direction between said electrodes, is formed within said matrix on application of a write voltage to said electrodes; an electrically-conductive component; wherein a resistance is presented by the electrically-conductive component; and wherein said RRAM is arranged such that said resistance is at least about that of said electrically-conductive path and at most about that of said electrically-insulating matrix in any of said plurality of programmable cell states.

First claim

We claim:

1 . A RRAM cell for storing information in a plurality of programmable cell states, the RRAM cell comprising:
an electrically-insulating matrix located between a first electrode and a second electrode such that an electrically-conductive path, extending in a direction between said electrodes, is formed within said matrix on application of a write voltage to said electrodes; and an electrically-conductive component; wherein a resistance is presented by said electrically-conductive component; and wherein said RRAM is arranged such that said resistance is at least about that of said electrically-conductive path and at most about that of said electrically-insulating matrix in any of said plurality of programmable cell states.

2 . The RRAM cell according to claim 1 , wherein a length of said insulating matrix in said direction between said electrodes is greater than a thickness of said matrix perpendicular to said direction.

3 . The RRAM cell according to claim 1 , wherein said RRAM cell is arranged such that said electrically-conductive path occupies at least about 10% of said thickness of said matrix perpendicular to said direction between said electrodes.

4 . The RRAM cell according to claim 1 , wherein said component comprises a layer of electrically-conductive material; and
wherein said layer of electrically-conductive material is disposed on one surface of said layer of insulating matrix.

5 . The RRAM cell according to claim 1 , wherein said component forms a sheath around said insulating matrix.

6 . The RRAM cell according to claim 5 , wherein said matrix forms an elongated core within said sheath.

7 . The RRAM cell according to claim 6 , wherein said elongated core comprises a nanowire of said insulating matrix.

8 . The RRAM cell according to claim 1 , further comprising:
an opposed layer of said insulating matrix extending in said direction between said electrodes; a core member extending in said direction between said electrodes in contact with respective inner surfaces of said opposed layers; and an outer member extending in said direction between said electrodes in contact with respective outer surfaces of said opposed layers; wherein said electrically conductive component comprises at least one of said core member and said outer member.

9 . The RRAM cell according to claim 8 , wherein said opposed layers join to form an annulus around said core member.

10 . The RRAM cell according to claim 1 , wherein said plurality of programmable cell states correspond to respective different lengths of said conductive path in said matrix.

11 . The RRAM cell according to claim 1 , wherein the resistance per unit length of said component varies in a direction between said electrodes.

12 . The RRAM cell according to claim 11 , wherein the shape of said component varies in a direction between the electrodes to vary the resistance per unit length.

13 . The RRAM cell according to claim 12 , wherein said component forms a sheath around said insulating matrix;
said matrix forms an elongated core within said sheath; and the thickness of said core increases in a direction in which thickness of said sheath decreases.

14 . The RRAM cell according to claim 11 , wherein said component comprises a plurality of alternating first sections and second sections in said direction between said electrodes; and
wherein said first sections are of lower resistance than said second sections to provide a stepped programming curve for said RRAM cell.

15 . The RRAM cell according to claim 1 for storing information:
in a first cell state in which the conductive path has a longer portion near said first electrode than said second electrode; and
in a second cell state in which the conductive path has a longer portion near said second electrode than said first electrode;
wherein said resistance per unit length, in said direction between said electrodes, of said component is greater near said first electrode than near said second.

16 . The RRAM cell according to claim 15 , wherein said component comprises a first section near said first electrode and a second section near said second electrode; and
wherein said first section has a higher resistivity than said second section.

17 . The RRAM cell according to claim 15 , wherein the shape of said component varies in said direction between said electrodes to vary said resistance per unit length.

18 . A complementary cell comprising:
an at least two RRAM cells, wherein said at least two RRAM cells are connected antiserially and electrically-conductive components of said at least two RRAM cells have a different electrical resistance: and wherein each said RRAM cell comprises: an electrically-insulating matrix located between a first electrode and a second electrode such that an electrically-conductive path, extending in a direction between said electrodes, is formed within said matrix on application of a write voltage to said electrodes; and an electrically-conductive component; wherein a resistance is presented by said electrically-conductive component; and wherein each said RRAM is arranged such that said resistance is at least about that of said electrically-conductive path and at most about that of said electrically-insulating matrix in any of said plurality of programmable cell states.

19 . A memory device comprising:
a read/write controller for reading and writing data in a plurality of RRAM cells; and wherein each said RRAM cell comprises: an electrically-insulating matrix located between a first electrode and a second electrode such that an electrically-conductive path, extending in a direction between said electrodes, is formed within said matrix on application of a write voltage to said electrodes; and an electrically-conductive component; wherein a resistance is presented by said electrically-conductive component; and wherein each said RRAM is arranged such that said resistance is at least about that of said electrically-conductive path and at most about that of said electrically-insulating matrix in any of said plurality of programmable cell states.

20 . A method for forming a RRAM cell for storing information in a plurality of programmable cell states, the method comprising:
forming a first electrode and a second electrode having an electrically-insulating matrix located therebetween such that an electrically-conductive path, extending in a direction between said electrodes, can be formed within said matrix on application of a write voltage to said electrodes; and forming an electrically-conductive component; wherein a resistance is presented by said electrically-conductive component; and wherein said RRAM is arranged such that said resistance is at least about that of said electrically-conductive path and at most about that of said electrically-insulating matrix in any of said plurality of programmable cell states.

Assignees

• IBM

Inventors

• Eleftheriou Evangelos S
• Krebs Daniel
• Sebastian Abu

Classifications

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• H01L45/16

  Electricity · mapped topic

• H01L27/2463

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic

• G11C13/0011 Primary

  comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs] · CPC title