Longest element length determination in memory

Patent metadata

Field	Value
Publication number	US-2016196856-A1
Application number	US-201514978583-A
Country	US
Kind code	A1
Filing date	Dec 22, 2015
Priority date	Jan 7, 2015
Publication date	Jul 7, 2016
Grant date	—

Abstract

Examples of the present disclosure provide apparatuses and methods for determining a length of a longest element in a memory. An example method comprises determining, using a controller to control sensing circuitry, a length of a longest element of a plurality of variable length elements of a vector stored in a memory array.

First claim

What is claimed is:

1 . A method, comprising:
determining, using a controller that controls sensing circuitry, a length of a longest element of a plurality of variable length elements of a vector stored in a memory array.

2 . The method of claim 1 , wherein determining the length of the longest element comprises an AND operation and a shift operation, wherein the AND operation and the shift operation is are based on the length of the longest element.

3 . The method of claim 2 , wherein the determining of the length of the longest element is performed in the memory array.

4 . The method of claim 2 , wherein the AND operation and the shift operation are each performed using sensing circuitry coupled to each of a number of columns of complementary sense lines.

5 . The method of claim 1 , wherein the determining of the length of the longest element comprises determining whether one or more of bits of each of the plurality of variable length elements includes a particular value.

6 . The method of claim 5 , wherein the particular value includes a bit value of 1.

7 . The method of claim 1 , comprising performing an operation on at least one element of the plurality of elements based on the length of the longest element.

8 . The method of claim 7 , wherein the operation is performed after the length of the longest element is determined.

9 . The method of claim 7 , wherein the operation is performed concurrent with the determination of the length of the longest element.

10 . The method of claim 1 , wherein the vector is stored in a group of memory cells coupled to a particular access line.

11 . The method of claim 10 , wherein a result of the determination of the length of the longest element is stored in a group of memory cells coupled to a different particular access line of the memory array.

12 . The method of claim 1 , wherein determining the length of the longest element comprises creating a static mask that indicates a most significant bit of each of the plurality of variable length elements.

13 . The method of claim 12 , wherein the static mask indicates a left-most boundary to begin performing the AND operation and the shift operation.

14 . An apparatus comprising:
a group of memory cells coupled to a first access line of a memory array and configured to store a plurality of variable length elements; and a controller configured to cause sensing circuitry to:
perform an AND operation and a SHIFT operation to determine a length of the longest element.

15 . The apparatus of claim 14 , wherein each of the sensing circuitry comprises a sense amplifier and a compute component.

16 . The apparatus of claim 15 , wherein each of the corresponding sense amplifiers comprises a primary latch and each of the corresponding compute components comprise a secondary latch.

17 . The apparatus of claim 14 , wherein the controller is configured to cause sensing circuitry to determine a most significant bit of each of the plurality of variable length elements.

18 . The apparatus of claim 17 , wherein the controller is configured to cause storing of elements representing the most significant bit of each of the plurality of variable length elements.

19 . The apparatus of claim 18 , wherein the controller is configured to cause sensing circuitry to perform an invert operation on the elements representing the most significant bit of each of the plurality of variable length elements.

20 . The apparatus of claim 19 , wherein the controller is configured to cause sensing circuitry to perform a shift operation on the inverted elements.

21 . The apparatus of claim 20 , wherein the shift operation is a left shift operation and a result of the shift operation is stored as a static mask in a group of cells coupled to a particular access line of the array.

22 . The apparatus of claim 14 , wherein the controller is further to perform a loop operation on the plurality of variable length elements.

23 . The apparatus of claim 22 , wherein the controller is configured to cause sensing circuitry to perform the loop operation by:
determining whether one or more bits of a mask indicating a most significant bit of each of the plurality of variable length elements include a particular value; and in response to one or more bits including the particular value:
performing a shift operation on the mask; and
performing an AND operation with the shifted mask and the mask indicating a most significant bit of each of the plurality of variable length elements.

24 . The apparatus of claim 23 , wherein the controller is configured to cause sensing circuitry to repeat the loop operation by:
determining whether one or more bits of a previously shifted mask includes a particular value; performing an additional shift operation on the previously shifted mask; and performing an additional AND operation with the previously shifted mask and the additionally shifted mask.

25 . A method, comprising:
determining, using a controller to control sensing circuitry, a length of a longest element of a plurality of variable length elements of a vector stored in a memory array by:
determining elements that indicate a most significant bit of each of the plurality of variable length elements;
determining a static mask by:
inverting the elements that indicate a most significant bit of each of the plurality of variable length elements; and
shifting the inverted elements; and

shifting the elements that indicate a most significant bit of each of the plurality of variable length elements.

26 . The method of claim 25 , comprising performing an operation on the plurality of variable length elements, wherein the operation performed is based on the length of the longest element.

27 . The method of claim 26 , comprising ANDing the shifted elements with the static mask.

28 . The method of claim 27 , comprising determining, subsequent to the ANDing operation, whether at least one bit of the elements is a particular value.

29 . The method of claim 28 , comprising, in response to at least one bit of the elements being a particular value, repeating a shift operation and an AND operation on the elements.

30 . The method of claim 29 , wherein the shift operation and the AND operation is repeated in response to a determination after each AND operation is performed that at least one bit of the previously shifted elements is the particular value.

31 . The method of claim 30 , comprising determining a length of the longest element of the plurality of variable length elements by counting a number of shift operations and AND operations performed in response to determining at least one bit of the shifted variable length elements is the particular value.

32 . A method, comprising:
determining, using a controller to control sensing circuitry in a memory array, how many times to perform an operation based on a length of a longest element of a plurality of variable length elements of a vector stored in a memory array by determining the length of the longest element by:
determining elements that indicate a most significant bit of each of the plurality of variable length elements;
determining a static mask by:
inverting the elements that indicate a most significant bit of each of the plurality of

Assignees

• Micron Technology Inc

Inventors

• Tiwari Sanjay
• Wheeler Kyle B

Classifications

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C7/1012 Primary

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title

• G11C11/4091

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G11C7/065 Primary

  Differential amplifiers of latching type · CPC title