Hardware accelerator and chip

Patent metadata

Field	Value
Publication number	US-2016196221-A1
Application number	US-201514981523-A
Country	US
Kind code	A1
Filing date	Dec 28, 2015
Priority date	Jan 4, 2015
Publication date	Jul 7, 2016
Grant date	—

Abstract

Present invention disclose a hardware accelerator and a chip, and the hardware accelerator includes: an interface circuit and an accelerator core coupled to the interface circuit, where the interface circuit is configured to receive a first task request, perform decoding on the first task request to acquire identifier information, and configure, according to the identifier information, the first task request to be in an FIFO queue that matches the identifier information; a scheduling controller is configured to determine, from at least two channel groups, one or more target channel groups that have at least one to-be-processed second task request in an n th period, receive a time parameter that is fed back by the accelerator core and corresponding to the target channel group, and schedule the at least one second task request in the one or more target channel groups according to the time parameter and a weighted round robin algorithm.

First claim

What is claimed is:

1 . A hardware accelerator, comprising: an interface circuit and an accelerator core coupled to the interface circuit, wherein the interface circuit comprises: an input/output (I/O) interface, a queue manager, and a scheduling controller; wherein
the I/O interface is configured to receive a first task request, wherein the first task request carries identifier information used to indicate a communications standard to which the first task request belongs, and a priority of the first task request; the queue manager comprises: a decoding circuit and at least two channel groups, wherein the at least two channel groups are respectively corresponding to at least two preset communications standards, each channel group is corresponding to one communications standard, any one of the channel groups comprises at least one first in first out (FIFO) queue, and the at least one FIFO queue is respectively corresponding to at least one preset priority; and the decoding circuit is configured to perform decoding on the first task request to acquire the identifier information, and configure, according to the identifier information, the first task request to be in a FIFO queue that matches the identifier information; the scheduling controller is configured to determine, from the at least two channel groups, one or more target channel groups that have at least one to-be-processed second task request in an n th period, receive a time parameter that is fed back by the accelerator core and corresponding to the target channel group, and schedule the at least one second task request in the one or more target channel groups according to the time parameter and a weighted round robin algorithm, wherein the n th period is any period in which the scheduling controller performs periodic scheduling on a task request in the at least two channel groups, and n is a natural number; and the accelerator core is configured to respond to the at least one scheduled second task request.

2 . The hardware accelerator according to claim 1 , wherein when the identifier information comprises a first virtual machine identifier (VMID) and a priority identifier (PID), wherein the first VMID indicates the communications standard to which the first task request belongs and the PID indicates the priority of the first task request,
the decoding circuit is specifically configured to: query a preset first address table according to the first VMID and the PID to determine a FIFO queue that matches the first VMID and the PID, and configure the first task request to be in the matched FIFO queue, wherein the first address table comprises a correspondence between each FIFO queue in the at least two channel groups, a preset VMID, and a preset PID.

3 . The hardware accelerator according to claim 1 , wherein when the identifier information comprises a VMID and an attribute identifier and the at least one FIFO queue is further respectively corresponding to a preset attribute identifier, wherein the VMID indicates the communications standard to which the first task request belongs and the attribute identifier indicates an attribute of the first task request,
the decoding circuit is specifically configured to: query a preset second address table according to the VMID and the attribute identifier to determine a FIFO queue that matches the VMID and the attribute identifier, and configure the first task request to be in the FIFO queue that matches the VMID and the attribute identifier, wherein the second address table comprises a correspondence between each FIFO queue in the at least two channel groups, a preset VMID, and a preset attribute identifier.

4 . The hardware accelerator according to claim 1 , wherein the scheduling controller comprises: a control unit, a scheduling unit, and a selecting unit, wherein
the selecting unit is configured to perform polling on the at least two channel groups to determine the one or more target channel groups from the at least two channel groups; the control unit is configured to receive the time parameter delay i that is fed back by the accelerator core and corresponding to the target channel group, and calculate respective weight values of the target channel groups according to the following formula:
W i =Duration i =Duration i′ +delay i /Rate i , wherein
W i is a weight value of any channel group i of the target channel groups, Duration i is accumulated processing time of task requests in the channel group i in the n th period, Duration i′ is accumulated processing time of the task requests in the channel group i in an (n−1) th period, delay i is processing time, in the accelerator core, of each task request in the channel group i in the (n−1) th period, Rate i is a ratio of a processing capability allocated to the channel group i to a processing capability allocated in advance by the accelerator core to the at least two channel groups, and i is a positive integer; and the scheduling unit is configured to read the at least one second task request to be processed in the one or more target channel groups in the n th period, perform, based on the respective weight values of the target channel groups, weighted round robin scheduling on the at least one second task request, and send the at least one scheduled second task request to the accelerator core.

5 . The hardware accelerator according to claim 4 , wherein the selecting unit is specifically configured to perform polling on all FIFO queues in the at least two channel groups, or configured to concurrently perform polling on each channel group of the at least two channel groups to determine the one or more target channel groups from the at least two channel groups.

6 . The hardware accelerator according to claim 4 , wherein when performing the weighted round robin scheduling on the at least one second task request, the scheduling unit performs the scheduling in ascending order of the respective weight values of the target channel groups.

7 . The hardware accelerator according to claim 4 , wherein the scheduling unit specifically comprises: a multiplexer switch and a scheduling circuit, wherein
the multiplexer switch is configured to separately convert the respective weight values of the target channel groups into control signals, sequentially select, in ascending order of the respective weight values of the target channel groups, a second task request in each target channel group and then send the second task request to the scheduling circuit; and the scheduling circuit is configured to separately schedule the second task request in each target channel group to the accelerator core in a priority-based and/or round robin scheduling manner.

8 . The hardware accelerator according to claim 2 , wherein the accelerator core is further configured to count a time parameter of each task request in the n th period and provide a feedback to the scheduling controller in an (n+1) th period, so that the scheduling controller performs next scheduling.

9 . The hardware accelerator according to claim 2 , wherein the interface circuit further comprises an interruption controller and an interruption interface, wherein the interruption controller comprises at least two interruption units, the at least two interruption units are corresponding, in a one-to-one manner, to the at least two communications standards, and any interruption unit of the at least two interruption units is configured to: receive interruption information sent by the accelerator core, and acquire, by querying a preset interruption information table, a VMID corresponding to the interruption information; and if the VMID corresponding to the interruption information is equal to a preset VMID of a channel group corres

Assignees

• Huawei Tech Co Ltd

Inventors

• Wan Yupeng

Classifications

• G06F13/1642 Primary

  with request queuing · CPC title

• G06F9/5027 Primary

  the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title

• G06F13/1673

  using buffers · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F2213/0038

  System on Chip · CPC title