Devices and Methods Implementing Operations for Selective Enforcement of Task Dependencies

Patent metadata

Field	Value
Publication number	US-2016196162-A1
Application number	US-201514792740-A
Country	US
Kind code	A1
Filing date	Jul 7, 2015
Priority date	Jan 7, 2015
Publication date	Jul 7, 2016
Grant date	—

Abstract

A method and computing device, for enabling selective enforcement of complex task dependencies. The method and allows a computing device to determine whether to enforce task-dependencies based on programmer or end-user goals concerning efficiency and quality of runtime experience. A computing device may be configured to schedule executing a first task, identify an operation (e.g., a “+>” operation) of the first task as being selectively dependent on a second task finishing execution, and determining whether to enforce the dependency of the first task on the second task based on an evaluation of one or more enforcement conditions. If the enforcement conditions are not met, enforcing the dependency, executing the second task, and withholding execution of the first task until execution of the second task has finished. If the enforcement conditions are met, commencing execution of the first task prior to, or parallel to the second task finishing execution.

First claim

What is claimed is:

1 . A method of executing tasks in a computing device, comprising implementing a first operator for selective enforcement of intertask execution dependencies.

2 . The method of claim 1 , further comprising implementing a second operation for mandatory enforcement of intertask execution dependencies.

3 . The method of claim 1 , wherein implementing a first operator for selective enforcement of intertask execution dependencies comprises:
commencing execution of a first task via a first thread of a thread pool in the computing device; identifying whether there exists a second task ready for execution such that an operation of the second task identifies the second task as either being dependent on the first task finishing execution or being selectively dependent on the first task finishing execution; identifying whether there exists a third task ready for execution such that an operation of the second task identifies the second task as either being dependent on the third task finishing execution or being selectively dependent on the third task finishing execution; commencing execution of the second task via a second thread of the thread pool only after determining that the third task has finished execution in response to identifying that there exists a third task ready for execution such that an operation of the second task identifies the second task as being dependent on the third task finishing execution; determining whether to enforce the selective dependency of the second task on the third task by determining whether one or more enforcement conditions are satisfied in response to identifying that there exists a third task ready for execution such that an operation of the second task identifies the second task as being selectively dependent on the third task finishing execution; ignoring the selective dependency, and commencing execution of the second task via a second thread of the thread pool in response to determining that the one or more enforcement conditions are met; and commencing execution of the second task via a second thread of the thread pool only after determining that the third task has finished execution in response to determining that the one or more enforcement conditions are not met, enforcing the selective dependency.

4 . A computing device, comprising:
a processor configured with processor-executable instructions to perform operations comprising implementing a first operation for selective enforcement of intertask execution dependencies.

5 . The computing of claim 4 , wherein the processor is configured with processor-executable instructions to perform operations further comprising implementing a second operation for mandatory enforcement of intertask execution dependencies.

6 . The computing device of claim 4 , wherein the processor is configured with processor-executable instructions to perform operations such that implementing a first operation for selective enforcement of intertask execution dependencies comprises:
commencing execution of a first task via a first thread of a thread pool in the computing device; identifying whether there exists a second task ready for execution such that an operation of the second task identifies the second task as either being dependent on the first task finishing execution or being selectively dependent on the first task finishing execution; identifying whether there exists a third task ready for execution such that an operation of the second task identifies the second task as either being dependent on the third task finishing execution or being selectively dependent on the third task finishing execution; commencing execution of the second task via a second thread of the thread pool only after determining that the third task has finished execution in response to identifying that there exists a third task ready for execution such that an operation of the second task identifies the second task as being dependent on the third task finishing execution; determining whether to enforce the selective dependency of the second task on the third task by determining whether one or more enforcement conditions are satisfied in response to identifying that there exists a third task ready for execution such that an operation of the second task identifies the second task as being selectively dependent on the third task finishing execution; ignoring the selective dependency, and commencing execution of the second task via a second thread of the thread pool in response to determining that the one or more enforcement conditions are met; and commencing execution of the second task via a second thread of the thread pool only after determining that the third task has finished execution in response to determining that the one or more enforcement conditions are not met, enforcing the selective dependency.

7 . The computing device of claim 6 , wherein the processor is configured with processor-executable instructions to perform operations such that implementing a first operation for selective enforcement of intertask execution dependencies comprises:
identifying whether any additional operations of the second task are either dependent or selectively dependent on any additional tasks other than the first task and third tasks finishing execution.

8 . The computing device of claim 6 , wherein the processor is configured with processor-executable instructions to perform operations such that implementing a first operation for selective enforcement of intertask execution dependencies comprises:
commencing execution of the second task via a second thread of the thread pool only after determining that additional tasks have finished execution in response to identifying that there exist additional tasks ready for execution such that an operation of the second task identifies the second task as being dependent on the additional tasks finishing execution.

9 . The computing device of claim 8 , wherein the processor is configured with processor-executable instructions to perform operations such that implementing a first operation for selective enforcement of intertask execution dependencies further comprises:
in response to identifying that there exist additional tasks ready for execution such that an operation of the second task identifies the second task as being selectively dependent on the additional tasks finishing execution:
determining whether to enforce the selective dependency of the second task on the additional tasks by determining whether the one or more enforcement conditions are satisfied;
ignoring the selective dependency and commencing execution of the second task via a second thread of the thread pool in response to determining that the one or more enforcement conditions are not met; and
enforcing the dependency and commencing execution of the second task via a second thread of the thread pool only after determining that the additional tasks have finished execution in response to determining that the one or more enforcement conditions are met.

10 . The computing device of claim 6 , wherein the processor is configured with processor-executable instructions to perform operations such that:
commencing execution of the first task via the first thread of the thread pool comprises executing the first task in a first processing core of the computing device; and commencing execution of the second task via the second thread of the thread pool comprises executing the second task in a second processing core of the computing device prior to or concurrent with execution of the first task in the first processing core.

11 . The computing device of claim 6 , wherein the processor is configured with processor-executab

Assignees

• Qualcomm Inc

Inventors

• Raman Arun
• Montesinos Ortego Pablo

Classifications

• G06F9/4881 Primary

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F9/4843 Primary

  by program, e.g. task dispatcher, supervisor, operating system · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F2209/484

  Precedence · CPC title