Array substrate and manufacturing method thereof, and display device

US2016195751A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016195751-A1
Application numberUS-201314357725-A
CountryUS
Kind codeA1
Filing dateDec 5, 2013
Priority dateJun 24, 2013
Publication dateJul 7, 2016
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate comprises a thin film transistor ( 202 ) on a base substrate ( 201 ), and an electrode structure ( 203 ) on the thin film transistor ( 202 ), and the electrode structure ( 203 ) includes a pixel electrode ( 2031 ) and a common electrode ( 2032 ) insulated from each other. The array substrate further comprises: a black matrix ( 204 ) disposed on the thin film transistor ( 202 ), an orthographic projection of the thin film transistor ( 202 ) on the base substrate ( 201 ) is located within an orthographic projection of the black matrix ( 204 ) on the base substrate ( 201 ), and the black matrix ( 204 ) is electrically connected with the common electrode ( 2032 ) for providing common electrode signals to the common electrode ( 2032 ).

First claim

Opening claim text (preview).

1 . An array substrate comprising a base substrate, a thin film transistor disposed on the base substrate, and an electrode structure disposed on the thin film transistor, the electrode structure comprising a pixel electrode and a common electrode insulated from each other, and the array substrate further comprising: a black matrix disposed on the thin film transistor, wherein an orthographic projection of the thin film transistor on the base substrate is located within an orthographic projection of the black matrix on the base substrate; and wherein the black matrix is electrically connected to the common electrode for providing common electrode signals to the common electrode. 2 . The array substrate according to claim 1 , wherein the black matrix is directly electrically connected to the common electrode. 3 . The array substrate according to claim 2 , wherein the black matrix is directly disposed on the common electrode. 4 . The array substrate according to claim 1 , wherein the black matrix is of a metallic material or a non-transparent organic conductive material. 5 . The array substrate according to claim 1 , wherein the array substrate comprises a plurality of pixel units and each pixel unit comprises the thin film transistor, the electrode structure and the black matrix; and wherein each pixel unit comprises a display region and a non-display region, the thin film transistor is located in the non-display region, a part of the electrode structure is disposed on the thin film transistor, and the other part of the electrode structure is located in the display region. 6 . The array substrate according to claim 1 , further comprising a color filter located between the thin film transistor and the electrode structure as an insulating layer. 7 . The array substrate according to claim 1 , further comprising a color filter located between the pixel electrode and the common electrode as an insulating layer. 8 . A display device comprising an array substrate according to claim 1 . 9 . A manufacturing method of an array substrate, comprising: a step of forming a thin film transistor on a base substrate; a step of forming an electrode structure, wherein the electrode structure comprises a pixel electrode and a common electrode insulated from each other; a step of forming a black matrix, wherein an orthographic projection of the thin film transistor on the base substrate is located within an orthographic projection of the black matrix on the base substrate, and the black matrix is directly electrically connected to the common electrode for providing common electrode signals to the common electrode. 10 . The manufacturing method according to claim 9 , wherein the step of forming the electrode structure and the step of forming the black matrix comprise: forming a pixel electrode on the thin film transistor; forming a common electrode which is insulated from the pixel electrode on the pixel electrode; forming a black matrix on the common electrode. 11 . The manufacturing method according to claim 10 , wherein forming the common electrode which is insulated from the pixel electrode on the pixel electrode and forming the black matrix on the common electrode comprise: forming the common electrode and the black matrix by one patterning process. 12 . The manufacturing method according to claim 11 , wherein forming the common electrode and the black matrix by one patterning process comprises: successively forming a thin film for the common electrode and a thin film for the black matrix; applying photoresist on the thin film for the black matrix, exposing and developing the photoresist by using a mask, and obtaining a photoresist-completely-removed region, a photoresist-partially-retained region and a photoresist-completely-retained region, wherein the photoresist-partially-retained region corresponds to a region for forming the common electrode and the photoresist-completely-retained region corresponds to a region for forming the black matrix; etching the photoresist-completely-removed region, the photoresist-partially-retained region and the photoresist-completely-retained region to form the common electrode and the black matrix. 13 . The manufacturing method according to claim 12 , wherein the mask is a half-tone mask or a gray-tone mask. 14 . The manufacturing method according to claim 12 , wherein etching the photoresist-completely-removed region, the photoresist-partially-retained region and the photoresist-completely-retained region to form the common electrode and the black matrix comprises: performing an etching process to etch off the thin film for the common electrode and the thin film for the black matrix of the photoresist-completely-removed region, and obtaining the common electrode; performing an ashing process on the photoresist to remove the photoresist in the photoresist-partially-retained region; performing an etching process to etch off the thin film for the black matrix in the photoresist-partially-retained region, removing the photoresist in the photoresist-completely-retained region and obtaining the black matrix. 15 . The manufacturing method according to claim 9 , wherein the black matrix is formed of a metallic material or a non-transparent organic conductive material. 16 . The manufacturing method according to claim 10 , wherein after forming the thin film transistor and before forming the pixel electrode, the method further comprises: forming a color filter serving as an insulating layer on the thin film transistor. 17 . The manufacturing method according to claim 9 , wherein after forming the pixel electrode and before forming the common electrode, the method further comprises: forming a color filter serving as an insulating layer on the pixel electrode. 18 . The array substrate according to claim 2 , wherein the black matrix is of a metallic material or a non-transparent organic conductive material. 19 . The array substrate according to claim 2 , wherein the array substrate comprises a plurality of pixel units and each pixel unit comprises the thin film transistor, the electrode structure and the black matrix; and wherein each pixel unit comprises a display region and a non-display region, the thin film transistor is located in the non-display region, a part of the electrode structure is disposed on the thin film transistor, and the other part of the electrode structure is located in the display region. 20 . The array substrate according to claim 2 , further comprising a color filter located between the thin film transistor and the electrode structure as an insulating layer.

Assignees

Inventors

Classifications

  • by modifying the pattern of conductive parts · CPC title

  • H10W20/077Primary

    on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

  • in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

  • Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element · CPC title

  • characterised by their geometrical arrangement · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2016195751A1 cover?
An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate comprises a thin film transistor ( 202 ) on a base substrate ( 201 ), and an electrode structure ( 203 ) on the thin film transistor ( 202 ), and the electrode structure ( 203 ) includes a pixel electrode ( 2031 ) and a common electrode ( 2032 ) insulated from each other. The array substra…
Who is the assignee on this patent?
Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W20/077. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jul 07 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).