Method and apparatus for calibration of a time interleaved adc

Patent metadata

Field	Value
Publication number	US-2016191071-A1
Application number	US-201514858793-A
Country	US
Kind code	A1
Filing date	Sep 18, 2015
Priority date	Apr 1, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

A system for calibrating time interleaved ADCs is disclosed and may include a time interleaved analog-to-digital converter (ADC) for converting analog signals to digital signals, the time interleaved ADC comprising: a plurality of active slices, and a plurality of reference slices, each reference slice associated with a corresponding one of the plurality of active slices. An output of each reference slice may be used to correct distortion in an output of the corresponding active slice. Each active slice may sample an input signal at a first rate and each associated reference slice may sample the input signal at a second rate, the second rate being slower than the first rate. Each sample taken by one of the plurality of reference slices may then be taken concurrent with a sample taken by the associated active slice. Each reference slice may include a reference sampling module and a dummy load.

First claim

1 - 23 . (canceled)

24 . A system for processing signals, said system comprising:
a time interleaved analog-to-digital converter (ADC) for converting analog signals to digital signals, said time interleaved ADC comprising:
a) a plurality of active slices; and
b) a plurality of reference slices, each reference slice associated with a corresponding one of the plurality of active slices;
wherein an output of each reference slice is used to correct distortion in an output of the corresponding active slice.

25 . The system of claim 24 , wherein the each active slice samples an input signal at a first rate and each associated reference slice samples the input signal at a second rate, the second rate being slower than the first rate and wherein each sample taken by one of the plurality of reference slices is taken concurrent with a sample taken by the associated active slice.

26 . The system of claim 25 , wherein each reference slice comprises a reference sampling module and a dummy load, the reference slice using the reference sampling module to sample the input signal and the dummy load providing a load to the input signal when the sampling module is not sampling the input concurrent with the active slice.

27 . The system of claim 26 , wherein the sampling module is a track and hold amplifier.

28 . The system of claim 26 , wherein at least one of the plurality of active slices includes a sampling module and an associated pipeline ADC coupled to the associated sampling module.

29 . The system of claim 28 , wherein at least one of the plurality of reference slices includes a successive approximation register (SAR) ADC associated with the reference sampling module, the SAR ADC being coupled to the associated reference sampling module.

30 . A system for processing signals, said system comprising:
a time interleaved analog-to-digital-converter (ADC), said ADC comprising:
a) a plurality of active slices, each active slice receiving an input signal, taking a sample of the input signal and outputting a digital value representing the input signal at a time the sample was taken;
b) a plurality of partial reference slices, each of the plurality of partial reference slices associated with a corresponding one of the active slices, each partial reference slice taking a sample of the input signal concurrent with the associated active slice; and
c) a shared portion of a reference slice coupled to each of the plurality of partial reference slices and receiving the samples taken by each partial reference slice, the shared portion of the reference slice servicing one of the plurality of partial reference slices at a time such that the combination of partial reference slice being serviced by the shared portion, and the shared portion of the reference slice, operate together to output a value representing the samples taken by the partial reference slice during the time the shared portion of the reference slice is servicing that partial reference slice.

31 . The system of claim 30 , wherein the shared portion of the reference slice comprises a successive approximation (SAR) module and a digital to analog converter (DAC), and at least one of the plurality of partial reference slices comprises a comparator to compare output of the DAC to the sample taken by the corresponding active slice.

32 . The system of claim 30 , further comprising an interleaver, the interleaver receiving each of the digital values representing the samples, calibrating the values from the active slices to reduce distortion due to differences between the active slices and interleaving the values to form a digital representation of the input signal.

33 . The system of claim 30 , wherein the each active slice samples an input signal at a first rate and each associated partial reference slice samples the input signal at a second rate, the second rate being slower than the first rate and wherein each sample taken by one of the plurality of partial reference slices is taken concurrent with a sample taken by the associated active slice.

34 . The system of claim 33 , wherein each partial reference slice comprises a reference sampling module and a dummy load, the partial reference slice using the reference sampling module to sample the input signal and the dummy load providing a load to the input signal when the sampling module is not sampling the input concurrent with the active slice.

35 . The system of claim 34 , wherein at least one of the plurality of active slices includes a sampling module and an associated pipeline ADC coupled to the associated sampling module.

36 . The system of claim 35 , wherein at least one of the plurality of partial reference slices includes a SAR ADC associated with the reference sampling module, the SAR ADC being coupled to the associated reference sampling module.

37 . The system of claim 36 , wherein the sample of the input signal taken by each partial reference slice is a sample of the sample taken by the associated active slice.

38 . A system for processing signals, said system comprising:
a time interleaved analog-to-digital converter (ADC), said time interleaved ADC comprising: a) a plurality of active slices, each active slice:
i. receiving an input signal,
ii. taking a sample of the input signal; and
iii. outputting a digital value representing the input signal at the time the sample was taken; and
b) a reference slice comprising:
i. a plurality of reference slice input modules, each reference slice input module associated with a corresponding one of the active slices, each reference slice input module taking a sample of the input signal concurrent with the at least one sample taken by the associated active slice; and
ii. a reference ADC, the reference ADC receiving the samples taken by each reference slice input module, the reference ADC servicing one of the plurality of reference slice input modules at a time by outputting a digital value representing the samples taken by the reference slice input module during the time the reference ADC is servicing that reference slice input module.

39 . The system of claim 38 , wherein the reference slice input module includes a sampling module.

40 . The system of claim 38 , wherein the reference slice input module includes a sampling module and a comparator, the comparator forming a part of the reference ADC.

41 . A method for processing signals, the method comprising:
in a time interleaved analog-to-digital converter (ADC) comprising a plurality of active slices, each with an associated reference slice:
a) receiving an analog signal in the plurality of active slices;
b) receiving the analog signal in the associated reference slices; and
c) correcting distortion in the digital output of at least one of the plurality of active slices using a digital output of the reference slice associated with the at least one active slice.

42 . The method of claim 41 , comprising:
a) sampling the analog signal at a first rate with each active slice; and b) sampling the analog signal at a second rate with each reference slice, the second rate being slower than the first rate, each sample taken by each of the plurality of reference slices being taken concurrent with a sample taken by the associated active slice.

43 . The method of claim 42 , comprising loading an output of each active slice with a dummy load during times when each active slice is taking a sample and the associated reference slice is not taking a sample.

44 . The

Assignees

• Luxtera Inc

Inventors

• Van Engelen Josephus
• Buchwald Aaron
• Duncan Ralph

Classifications

• H03M1/0675

  using redundancy · CPC title

• H03M1/14

  Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit · CPC title

• H03M1/0678

  using additional components or elements, e.g. dummy components · CPC title

• H03M1/1215

  using time-division multiplexing · CPC title

• H03M1/124

  Sampling or signal conditioning arrangements specially adapted for A/D converters · CPC title