Circuit, a time-to-digital converter, an integrated circuit, a transmitter, a receiver and a transceiver
US-2015372690-A1 · Dec 24, 2015 · US
Analog-to-digital converter for correcting error and analog-to-digital converting method
US2016191069A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016191069-A1 |
| Application number | US-201514660667-A |
| Country | US |
| Kind code | A1 |
| Filing date | Mar 17, 2015 |
| Priority date | Dec 29, 2014 |
| Publication date | Jun 30, 2016 |
| Grant date | — |
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Abstract
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An analog-to-digital converter includes an upper bit conversion unit suitable for receiving an input signal, and sampling upper bits from the input signal, a lower bit conversion unit suitable for receiving a residual voltage remaining after the sampling of the upper bit conversion unit, and sampling lower bits from the residual voltage, and an error correction unit suitable for correcting an error of the sampled upper bits and the sampled lower bits.
First claim
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1 . An analog-to-digital converter comprising: an upper bit conversion unit suitable for receiving an input signal, sampling upper bits from the input signal, and providing a residual voltage remaining after the sampling the upper bits to a lower bit conversion unit in synchronization with a ramp signal; the lower bit conversion unit suitable for generating the ramp signal having a step waveform, providing the ramp signal to the upper bit conversion unit, receiving the residual voltage from,…
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Electricity · mapped topic
- H03M1/08Primary
Electricity · mapped topic
Electricity · mapped topic
- H03M1/0695Primary
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US2016191069A1 cover?
- An analog-to-digital converter includes an upper bit conversion unit suitable for receiving an input signal, and sampling upper bits from the input signal, a lower bit conversion unit suitable for receiving a residual voltage remaining after the sampling of the upper bit conversion unit, and sampling lower bits from the residual voltage, and an error correction unit suitable for correcting an e…
- Who is the assignee on this patent?
- Sk Hynix Inc, Iucf Hyu
- What technology area does this patent fall under?
- Primary CPC classification H03M1/08. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Jun 30 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).