Semiconductor Device, Display Device, Display Module, Electronic Device, Oxide, and Manufacturing Method of Oxide

Patent metadata

Field	Value
Publication number	US-2016190346-A1
Application number	US-201514974977-A
Country	US
Kind code	A1
Filing date	Dec 18, 2015
Priority date	Dec 26, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

The semiconductor device includes a first insulator over a substrate, a first oxide semiconductor over the first insulator, a second oxide semiconductor over the first oxide semiconductor, a first conductor and a second conductor in contact with the second oxide semiconductor, a third oxide semiconductor on the second oxide semiconductor and the first and second conductors, a second insulator over the third oxide semiconductor, and a third conductor over the second insulator. At least one of the first oxide semiconductor, the second oxide semiconductor, and the third oxide semiconductor has a crystallinity peak that corresponds to a (hkl) plane (h=0, k=0, l is a natural number) observed by X-ray diffraction using a Cu K-alpha radiation as a radiation source. The peak appears at a diffraction angle 2 theta greater than or equal to 31.3 degrees and less than 33.5 degrees.

First claim

1 . A semiconductor device comprising:
a transistor comprising:
a first oxide semiconductor; and
a second oxide semiconductor over the first oxide semiconductor,
wherein at least one of the first oxide semiconductor and the second oxide semiconductor has a crystallinity peak that corresponds to a (hkl) plane, where h is 0, k is 0, and l is a natural number, observed by X-ray diffraction using a Cu Kα radiation as a radiation source, and wherein the peak appears at a diffraction angle 2θ greater than or equal to 31.3° and less than 33.50.

2 . The semiconductor device according to claim 1 , wherein the peak appears at a diffraction angle 2θ greater than or equal to 31.8° and less than 32.8°.

3 . The semiconductor device according to claim 1 , wherein lattice spacing in at least one of the first oxide semiconductor and the second oxide semiconductor is longer than or equal to 0.27 nm and shorter than or equal to 0.28 nm in a normal direction of a surface of the first oxide semiconductor or a surface of the second oxide semiconductor.

4 . The semiconductor device according to claim 1 ,
wherein the transistor comprises:
a first conductor;
a first insulator over the first conductor;
the first oxide semiconductor over the first insulator;
the second oxide semiconductor over the first oxide semiconductor; and
a second conductor and a third conductor in contact with the second oxide semiconductor.

5 . The semiconductor device according to claim 1 ,
wherein the transistor comprises:
a first conductor;
a first insulator over the first conductor;
the first oxide semiconductor over the first insulator;
the second oxide semiconductor over the first oxide semiconductor;
a third oxide semiconductor over the second oxide semiconductor; and
a second conductor and a third conductor in contact with the third oxide semiconductor.

6 . The semiconductor device according to claim 1 ,
wherein the transistor comprises:
a first insulator;
the first oxide semiconductor over the first insulator;
the second oxide semiconductor over the first oxide semiconductor;
a first conductor and a second conductor in contact with the second oxide semiconductor;
a third oxide semiconductor on the second oxide semiconductor, the first conductor, and the second conductor,
a second insulator over the third oxide semiconductor; and
a third conductor over the second insulator.

7 . A display device comprising:
the semiconductor device according to claim 1 ; and a display element.

8 . A display module comprising:
the display device according to claim 7 ; and a touch sensor.

9 . An electronic device comprising:
the display module according to claim 8 ; and an operation key or a battery.

10 . A manufacturing method of an oxide,
wherein the manufacturing method is a sputtering method using a deposition chamber, a pair of targets positioned in the deposition chamber, and magnets for making a space between the pair of targets a magnetic field space, wherein the pair of targets comprises indium, zinc, an element M, and oxygen, wherein the element M is at least any one of aluminum, gallium, yttrium, and tin, and wherein the manufacturing method comprising the steps of:
placing a substrate between the pair of targets;
supplying a sputtering gas comprising oxygen or a rare gas to the deposition chamber;
adjusting pressure in the deposition chamber to higher than or equal to 0.005 Pa and lower than or equal to 0.09 Pa;
supplying a sputtering power to the pair of targets to generate plasma;
sputtering the pair of targets using ions in the plasma; and
depositing particles sputtered from the pair of targets on the substrate.

11 . The manufacturing method of an oxide, according to claim 10 , wherein the substrate is placed in a positive column of the plasma.

12 . The manufacturing method of an oxide, according to claim 10 , wherein L 1 and L 2 are each longer than or equal to 10 mm and shorter than or equal to 200 mm, where L 1 is a horizontal distance from one of the pair of targets to the substrate and L 2 is a horizontal distance from the other of the pair of targets to the substrate.

13 . The manufacturing method of an oxide, according to claim 10 , wherein temperature of the substrate during deposition is higher than or equal to 10° C. and lower than 100° C.

14 . The manufacturing method of an oxide, according to claim 10 , wherein temperature of the substrate during deposition is higher than or equal to 100° C. and lower than or equal to 500° C.

15 . The manufacturing method of an oxide, according to claim 10 , wherein the oxide is formed over a surface of an amorphous structure.

16 . The manufacturing method of an oxide, according to claim 10 , wherein lattice spacing in the oxide is longer than or equal to 0.27 nm and shorter than or equal to 0.28 nm in a normal direction of the substrate.

17 . A manufacturing method of an oxide,
wherein the manufacturing method is a sputtering method using a deposition chamber, a pair of targets positioned in the deposition chamber, and magnets for making a space between the pair of targets a magnetic field space, wherein the pair of targets comprises indium, zinc, an element M, and oxygen, wherein the element M is at least any one of aluminum, gallium, yttrium, and tin, and wherein the manufacturing method comprising the steps of:
placing a substrate beside the space between the pair of targets;
supplying a sputtering gas comprising oxygen or a rare gas to the deposition chamber;
adjusting pressure in the deposition chamber to higher than or equal to 0.005 Pa and lower than or equal to 0.09 Pa;
supplying a sputtering power to the pair of targets to generate plasma;
sputtering the pair of targets using ions in the plasma; and
depositing particles sputtered from the pair of targets on the substrate.

18 . The manufacturing method of an oxide, according to claim 17 , wherein the substrate is placed in a positive column of the plasma.

19 . The manufacturing method of an oxide, according to claim 17 , wherein L 1 and L 2 are each longer than or equal to 10 mm and shorter than or equal to 200 mm, where L 1 is a horizontal distance from one of the pair of targets to the substrate and L 2 is a horizontal distance from the other of the pair of targets to the substrate.

20 . The manufacturing method of an oxide, according to claim 17 , wherein temperature of the substrate during deposition is higher than or equal to 10° C. and lower than 100° C.

21 . The manufacturing method of an oxide, according to claim 17 , wherein temperature of the substrate during deposition is higher than or equal to 100° C. and lower than or equal to 500° C.

22 . The manufacturing method of an oxide, according to claim 17 , wherein the oxide is formed over a surface of an amorphous structure.

23 . The manufacturing method of an oxide, according to claim 17 , wherein lattice spacing in the oxide is longer than or equal to 0.27 nm and shorter than or equal to 0.28 nm in a normal direction of the substrate.

Assignees

• Semiconductor Energy Lab

Inventors

• Kawata Takuya
• Oota Masashi
• Nonaka Yusuke
• Yamazaki Shunpei

Classifications

• C23C14/564

  Means for minimising impurities in the coating chamber such as dust, moisture, residual gases · CPC title

• H01J37/3447

  Collimators, shutters, apertures · CPC title

• H01J37/3408

  Planar magnetron sputtering · CPC title

• H01J37/3417

  Arrangements · CPC title

• C23C14/08

  Oxides (C23C14/10 takes precedence) · CPC title