Split-gate trench power mosfet with protected shield oxide

Patent metadata

Field	Value
Publication number	US-2016190265-A1
Application number	US-201615061912-A
Country	US
Kind code	A1
Filing date	Mar 4, 2016
Priority date	Dec 12, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.

First claim

We claim:

1 . A semiconductor device, comprising:
a plurality of gate trenches formed into a semiconductor substrate in an active cell region, each gate trench having a first conductive material in lower portions of the gate trench and a second conductive material in upper portions of the gate trench, wherein the first conductive material in the gate trench is separated from the semiconductor substrate by a first insulating layer, and wherein the second conductive material in the gate trench is separated from the semiconductor substrate by a second insulating layer and separated from the first conductive material in the gate trench by a third insulating layer; and one or more other trenches formed into the semiconductor substrate in a region other than the active cell region, wherein the one or more other trenches contain at least part of the first conductive material in a half U shape in lower portions of the one or more trenches and part of the second conductive material in upper portions of the one or more other trenches, and wherein the first conductive material and the second conductive material in the one or more other trenches are separated by the third insulating layer.

2 . The device of claim 1 , wherein the semiconductor substrate is an N-type semiconductor substrate.

3 . The device of claim 1 , wherein the semiconductor substrate is a P-type semiconductor substrate.

4 . The device of claim 1 , further comprising one or more pickup trenches formed into the semiconductor substrate in a pickup region, wherein the one or more pickup trenches are connected to the one or more gate trenches, wherein the one or more pickup trenches contain at least part of the first conductive material with the first insulating layer separating the part of the first conductive material in the one or more pickup trenches from the semiconductor substrate.

5 . The device of claim 1 , wherein the one or more other trenches each has part of the first insulating layer lining along bottom and at least one sidewall of the trench.

6 . The device of claim 1 , wherein the one or more other trenches formed into the semiconductor substrate in a region other than the active cell region are peripheral trenches in a peripheral region, wherein the peripheral region is provided between the active cell region and an edge of the device.

7 . The device of claim 6 , wherein the part of the second conductive material in the peripheral trenches is separated from the semiconductor substrate by the second insulating material.

8 . The device of claim 6 , wherein each of the peripheral trenches has asymmetrical sidewall insulation with a first insulating layer on a side adjacent to the edge of the device and a second insulating layer on a side adjacent to the active cell region.

9 . The device of claim 1 , wherein the one or more other trenches formed into the semiconductor substrate in a region other than the active cell region are transitional trenches in a pickup region, wherein the transitional trenches are provided between the plurality of gate trenches and a pickup trench.

10 . The device of claim 9 , wherein a part of the first conductive material in lower portions of the transitional trenches is in a U shape.

11 . The device of claim 9 , wherein a part of the third insulating layer in the transitional trenches is in a U shape.

12 . The device of claim 1 , wherein the first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second insulating layer.

13 . A method for fabricating a semiconductor device, comprising:
forming a plurality of gate trenches into a semiconductor substrate in an active cell region, each gate trench having a first conductive material in lower portions of the gate trench and a second conductive material in upper portions of the gate trench, wherein the first conductive material in the gate trench is separated from the semiconductor substrate by a first insulating layer, and wherein the second conductive material in the gate trench is separated from the semiconductor substrate by a second insulating layer and separated from the first conductive material in the gate trench by a third insulating layer; and forming one or more other trenches into the semiconductor substrate in a region other than the active cell region, wherein each other trench is filled with the first conductive material in a half U shape in lower portions of the one or more trenches and the second conductive material in upper portions of the one or more trenches, and wherein the first conductive material and the second conductive material in the one or more trenches are separated by the third insulating layer.

14 . The method of claim 13 , wherein the first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second insulating layer.

15 . The method of claim 13 , further comprising forming one or more pickup trenches connected to the one or more gate trenches, wherein the one or more pickup trenches contain at least part of the first conductive material with a first insulating layer separating the part of the first conductive material in the one or more pickup trenches from the semiconductor substrate.

16 . The method of claim 15 , wherein each of the one or more gate trenches, one or more pickup trenches, and one or more other trenches, has part of the first insulating layer lining a bottom and at least one sidewall of the trench.

17 . The method of claim 15 , wherein the one or more other trenches include a trench located between the active cell region and an edge of the device.

18 . The method of claim 13 , further comprising forming one or more peripheral trenches in a peripheral region between the active cell region and an edge of the semiconductor device, wherein the one or more peripheral trenches each has a half U-shaped first conductive region.

19 . The method of claim 18 , wherein the part of a second conductive material in the peripheral trenches is separated from the semiconductor substrate by the second insulating material.

20 . The method of claim 19 , wherein each of the peripheral trenches has asymmetrical sidewall insulation with the first insulating layer on a side adjacent to the edge of the device and a second insulating layer on a side adjacent to the active cell region.

21 . The method of claim 15 , wherein the one or more other trenches are provided between the plurality of gate trenches and a pickup trench.

22 . The method of claim 21 , wherein a part of the first conductive material in lower portions of the other trenches is in a U shape.

23 . The method of claim 22 , wherein a part of an intermediate dielectric region in the other trenches is in a U shape.

Assignees

• Alpha & Omega Semiconductor

Inventors

• Lee Yeeheng
• Guan Lingpeng
• Xue Hongyong
• Gu Yiming
• Xiang Yang
• Huang Terence
• Ramamoorthy Sekar
• Li Wenjun
• Chang Hong
• Bobde Madhur
• Thorup Paul
• Yilmaz Hamza

Classifications

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title

• H10D64/514

  characterised by the insulating layers · CPC title