Interconnection structure and manufacturing method thereof

US2016190062A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016190062-A1
Application numberUS-201514850848-A
CountryUS
Kind codeA1
Filing dateSep 10, 2015
Priority dateDec 30, 2014
Publication dateJun 30, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An interconnection structure includes a first dielectric layer, a first conductor, an etch stop layer, a second dielectric layer, and a second conductor. The first dielectric layer has at least one hole therein. The first conductor is disposed at least partially in the hole of the first dielectric layer. The etch stop layer is disposed on the first dielectric layer. The etch stop layer has an opening to at least partially expose the first conductor. The second dielectric layer is disposed on the etch stop layer and has at least one hole therein. The hole of the second dielectric layer is in communication with the opening of the etch stop layer. The second conductor is disposed at least partially in the hole of the second dielectric layer and is electrically connected to the first conductor through the opening of the etch stop layer.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method for manufacturing an interconnection structure, the method comprising: forming at least one first hole in a first dielectric layer; forming a first conductor in the first hole; etching back the first dielectric layer, such that the first conductor has a portion protruding from the first dielectric layer; forming an etch stop layer on the first dielectric layer and the protruding portion of the first conductor; forming a second dielectric layer on the etch stop layer; forming at least one second hole through the second dielectric layer and the etch stop layer, such that the protruding portion of the first conductor is at least partially exposed by the second hole; and forming a second conductor in the second hole. 2 . The method of claim 1 , wherein the forming the second hole comprises: etching a top hole in the second dielectric layer; and etching an opening in the etch stop layer, such that the protruding portion of the first conductor is at least partially exposed by the opening, wherein the opening and the top hole are in communication with each other to form the second hole. 3 . The method of claim 2 , wherein the etch stop layer has higher etch resistance to an etchant used to etch the top hole in the second dielectric layer than that of the second dielectric layer. 4 . The method of claim 2 , wherein the etch stop layer has higher etch resistance to an etchant used to etch the top hole in the second dielectric layer than that of the first dielectric layer. 5 . The method of claim 2 , wherein the etching the opening is stopped before reaching the first dielectric layer. 6 . An interconnection structure, comprising: a first dielectric layer having at least one hole therein; a first conductor disposed at least partially in the hole of the first dielectric layer; an etch stop layer disposed on the first dielectric layer, the etch stop layer having an opening to at least partially expose the first conductor; a second dielectric layer disposed on the etch stop layer and having at least one hole therein, wherein the hole of the second dielectric layer is in communication with the opening of the etch stop layer; and a second conductor disposed at least partially in the hole of the second dielectric layer and electrically connected to the first conductor through the opening of the etch stop layer. 7 . The interconnection structure of claim 6 , wherein the etch stop layer and the second dielectric layer have different etch resistance properties. 8 . The interconnection structure of claim 6 , wherein the etch stop layer and the first dielectric layer have different etch resistance properties. 9 . The interconnection structure of claim 6 , wherein the etch stop layer is made of a carbon-rich material. 10 . The interconnection structure of claim 6 , wherein the first dielectric layer has a top surface facing the etch stop layer, and the first conductor has a portion protruding from the top surface of the first dielectric layer. 11 . The interconnection structure of claim 6 , further comprising: a third conductor disposed partially in the first dielectric layer, wherein the first dielectric layer has a top surface facing the etch stop layer, the third conductor has a portion protruding from the top surface of the first dielectric layer, and the etch stop layer covers the protruding portion of the third conductor. 12 . The interconnection structure of claim 11 , wherein the etch stop layer has a raised portion covering the protruding portion of the third conductor, the raised portion has a cap part covering a top surface of the protruding portion of the third conductor and at least one spacer part disposed on at least one sidewall of the protruding portion of the third conductor, and the spacer part is thicker than the cap part. 13 . The interconnection structure of claim 6 , wherein the etch stop layer has a portion disposed between the second conductor and the first dielectric layer. 14 . An interconnection structure, comprising: a first dielectric layer; at least one first conductor disposed at least partially in the first dielectric layer; a second dielectric layer having a hole therein; a third dielectric layer disposed between the first dielectric layer and the second dielectric layer, the third dielectric layer having an opening in communication with the hole of the second dielectric layer, wherein the first conductor is at least partially exposed by the opening of the third dielectric layer, and the third dielectric layer has higher etch resistance to an etchant used to etch the hole of the second dielectric layer than that of the second dielectric layer; and a second conductor electrically connected to the first conductor through the hole of the second dielectric layer and the opening of the etch stop layer. 15 . The interconnection structure of claim 14 , wherein the third dielectric layer has higher etch resistance to the etchant used to etch the hole of the second dielectric layer than that of the first dielectric layer. 16 . The interconnection structure of claim 14 , wherein the third dielectric layer is made of a carbon-rich material. 17 . The interconnection structure of claim 14 , wherein the first conductor has a portion protruding from the first dielectric layer. 18 . The interconnection structure of claim 14 , further comprising: a third conductor disposed partially in the first dielectric layer and having a portion protruding from the first dielectric layer. 19 . The interconnection structure of claim 18 , wherein the third dielectric layer has a raised portion covering the protruding portion of the third conductor, the raised portion has a cap part covering a top surface of the protruding portion of the third conductor and at least one spacer part disposed on at least one sidewall of the protruding portion of the third conductor, and the spacer part is thicker than the cap part. 20 . The interconnection structure of claim 14 , wherein the first dielectric layer is not exposed by the opening of the third dielectric layer.

Assignees

Inventors

Classifications

  • by forming conductive members before forming protective insulating material · CPC title

  • Cross-sectional shapes or dispositions of interconnections · CPC title

  • H10W20/081Primary

    by forming openings in the dielectric parts · CPC title

  • on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

  • H10W20/056Primary

    by filling conductive material into holes, grooves or trenches · CPC title

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What does patent US2016190062A1 cover?
An interconnection structure includes a first dielectric layer, a first conductor, an etch stop layer, a second dielectric layer, and a second conductor. The first dielectric layer has at least one hole therein. The first conductor is disposed at least partially in the hole of the first dielectric layer. The etch stop layer is disposed on the first dielectric layer. The etch stop layer has an o…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W20/081. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jun 30 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).