Integrated circuits with inactive gates and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016190012-A1
Application number	US-201414585250-A
Country	US
Kind code	A1
Filing date	Dec 30, 2014
Priority date	Dec 30, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

Integrated circuits and methods for manufacturing the same are provided. A method for producing an integrated circuit includes forming a first active dummy gate, a second active dummy gate, and an inactive gate overlying a substrate. The first active dummy gate is replaced with a first metal gate, where replacing the first active dummy gate includes planarizing the first metal gate, the second active dummy gate, and the inactive gate. The second active dummy gate is replaced with a second replacement metal after the first active dummy gate was replaced, where the inactive gate remains overlying the substrate.

First claim

What is claimed is:

1 . A method of manufacturing an integrated circuit comprising:
forming a first active dummy gate, a second active dummy gate, and an inactive gate overlying a substrate; replacing the first active dummy gate with a first metal gate, wherein replacing the first active dummy gate comprises planarizing the first metal gate, the second active dummy gate, and the inactive gate; and replacing the second active dummy gate with a second metal gate after replacing the first active dummy gate, wherein the inactive gate remains overlying the substrate after replacing the second active dummy gate.

2 . The method of claim 1 wherein forming the first active dummy gate, the second active dummy gate, and the inactive gate comprises forming the first active dummy gate, the second active dummy gate, and the inactive gate comprising polysilicon.

3 . The method of claim 1 wherein replacing the second active dummy gate comprises maintaining the inactive gate comprising polysilicon as the inactive gate having an inactive gate area, wherein the inactive gate area is about 0.1 percent or more of a tile area.

4 . The method of claim 1 further comprising:
sectioning the integrated circuit into a tile area; and
wherein replacing the second active dummy gate with the second metal gate comprises maintaining the inactive gate comprising polysilicon with an inactive gate area, and wherein the inactive gate area is from about 3 to about 6 percent of the tile area when a total gate area is more than about 65 percent to about 70 percent of the tile area.

5 . The method of claim 4 wherein sectioning the integrated circuit into the tile area comprises sectioning the integrated circuit into a plurality of tile areas, wherein the plurality of tile areas are formed with a 50 percent step, such that a second tile area overlaps a first tile area by about 50 percent.

6 . The method of claim 1 wherein replacing the second active dummy gate with the second metal gate comprises forming the second metal gate with a second metal gate height that is within about 10 percent of a first metal gate height.

7 . The method of claim 1 further comprising:
forming a dielectric layer overlying the substrate, wherein the dielectric layer is adjacent to the first active dummy gate and the second active dummy gate.

8 . The method of claim 1 further comprising:
maintaining the inactive gate comprising polysilicon when replacing the second active dummy gate.

9 . The method of claim 1 further comprising:
forming a gate dielectric between each of the first active dummy gate and the substrate, the second active dummy gate and the substrate, and the inactive gate and the substrate.

10 . The method of claim 1 further comprising:
forming a pFET with the first metal gate.

11 . The method of claim 1 wherein forming the inactive gate comprises forming the inactive gate within about 70 microns of the first active dummy gate.

12 . The method of claim 1 further comprising:
forming an interlayer dielectric overlying the first metal gate, the second metal gate, and the inactive gate; and
forming a contact through the interlayer dielectric, wherein the contact is in electrical connection with the first metal gate.

13 . A method of manufacturing an integrated circuit comprising:
forming a first active dummy gate, a second active dummy gate, and an inactive gate overlying a substrate; replacing the first active dummy gate with a first metal gate; replacing the second active dummy gate with a second metal gate after replacing the first active dummy gate with the first metal gate, wherein the inactive gate remains overlying the substrate, and wherein an inactive gate area is about 0.1 percent or more of a tile area.

14 . The method of claim 13 wherein replacing the second active dummy gate comprises maintaining the inactive gate comprising polysilicon having the inactive gate area of about 0.1 percent or more.

15 . The method of claim 13 wherein replacing the first active dummy gate comprises planarizing the first metal gate, the second active dummy gate, and the inactive gate.

16 . The method of claim 13 wherein replacing the second active dummy gate comprises forming the second metal gate with a second metal gate height within about 10 percent of a first metal gate height.

17 . The method of claim 13 wherein replacing the second active dummy gate comprises maintaining the inactive gate comprising polysilicon having the inactive gate area of from about 3 to about 6 percent of the tile area, and where a total gate area is from more than about 65 to about 70 percent of the tile area.

18 . The method of claim 13 wherein replacing the second active dummy gate comprises maintaining the inactive gate comprising polysilicon having the inactive gate area of from about 0.1 to about 3 percent of the tile area, and wherein a total gate area is from about 60 to about 65 percent of the tile area.

19 . The method of claim 13 further comprising:
forming an interlayer dielectric overlying the first metal gate, the second metal gate, and the inactive gate; and
Forming a contact in electrical connection with the first metal gate.

20 . An integrated circuit comprising:
a first metal gate overlying a substrate, wherein the first metal gate comprises a first conductive core; a second metal gate overlying the substrate, wherein the second metal gate comprises a second conductive core; an inactive gate overlying the substrate, wherein the inactive gate comprises polysilicon, and wherein the inactive gate is within about 70 microns of the first metal gate; and an interlayer dielectric overlying the substrate.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Zhu Ming
• Nga Yiang Aun

Classifications

• H10P95/04

  Planarisation of conductive or resistive materials · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D84/0177

  the gate conductors having different materials or different implants · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title