Semiconductor memory and system using the same

Patent metadata

Field	Value
Publication number	US-2016189802-A1
Application number	US-201514636917-A
Country	US
Kind code	A1
Filing date	Mar 3, 2015
Priority date	Dec 30, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

A semiconductor memory may include a plurality of stacked semiconductor chips which are interconnected using through-chip vias. The semiconductor memory may set chip IDs of the respective semiconductor chips by using a chip code such that the chip IDs are different from each other, and perform a through-chip via test for the plurality of stacked semiconductor chips by changing the chip IDs of the respective semiconductor chips during a test mode period.

First claim

What is claimed is:

1 . A semiconductor memory comprising a plurality of stacked semiconductor chips which are interconnected using through-chip vias,
wherein the semiconductor memory sets chip IDs of respective semiconductor chips by using a chip code such that the chip IDs are different from each other, and performs a through-chip via test for the plurality of stacked semiconductor chips by changing the chip IDs of the respective semiconductor chips during a test mode period.

2 . The semiconductor memory according to claim 1 , wherein the semiconductor memory changes the chip IDs of the respective chips during the test mode period by transmitting an external code through the same transmission code as a transmission path of the chip code.

3 . The semiconductor memory according to claim 1 , wherein, when performing the through-chip via test, the semiconductor memory changes the chip IDs of the respective chips so that, among the plurality of stacked semiconductor chips, a desired memory chip has a certain chip ID which is supposed to electrically connected to a current source and a current for the through-chip via test flows through a through-chip via coupled to the desired memory chip.

4 . The semiconductor memory according to claim 1 , wherein one of the plurality of chips is a logic chip, and
the logic chip is configured to set a chip ID thereof to an initial value, and transmit the chip ID or the external code as the chip code to an upper chip.

5 . The semiconductor memory according to claim 1 , wherein the plurality of chips comprise a logic chip and a plurality of memory chips stacked over the logic chip, and
each of the memory chips is configured to set a value obtained by adding a predetermined value to the chip code provided from a lower chip, as the chip ID thereof.

6 . The semiconductor memory according to claim 1 , wherein the plurality of chips comprise a logic chip and a plurality of memory chips stacked over the logic chip, and
each of the memory chips is configured to activate a current source thereof, when a value obtained by adding a predetermined value to the chip code provided from a lower chip coincides with a target value.

7 . The semiconductor memory according to claim 1 , wherein each of the plurality of chips excluding the lowermost chip comprises:
a plurality of through-chip vias; and an ID setup and test unit configured to set the chip ID of the chip using the chip code provided from a lower chip according to whether the current mode is a test mode, or perform a test for the plurality of through-chip vias.

8 . The semiconductor memory according to claim 1 , wherein each of the plurality of chips excluding the lowermost chip comprises:
a plurality of through-chip vias; a current source coupled to the plurality of through-chip vias; an adder configured to add a predetermined value to the chip code; and a logic element configured to activate the current source when an output of the adder coincides with a target value.

9 . The semiconductor memory according to claim 8 , further comprising a comparator configured to compare an external code inputted in a normal mode to the output of the adder, and determine whether to select a chip.

10 . A system comprising:
a semiconductor memory configured to set chip IDs of a plurality of stacked semiconductor chips by using a chip code such that the chip IDs are different from each other, and perform a through-chip via test for the plurality of stacked semiconductor chips by changing the chip IDs of the respective semiconductor chips during a test mode period; a processor configured to provide external codes, which vary according to the number of the plurality of chips in the semiconductor memory, to the semiconductor memory to perform the through-chip via test; and a substrate configured to provide a signal path for communication between the processor and the semiconductor memory.

11 . The system according to claim 10 , wherein the processor is configured to communicate with a host through the substrate.

12 . The system according to claim 10 , wherein the semiconductor memory is configured to change the chip IDs of the respective chips during the test mode period by transmitting the external codes through the same transmission code as a transmission code of the chip code.

13 . The system according to claim 10 , wherein, when performing the through-chip via test, the semiconductor memory changes the chip IDs of the respective chips so that, among the plurality of stacked semiconductor chips, a desired memory chip has a certain chip ID which is supposed to electrically connected to a current source and a current for the through-chip via test flows through a through-chip via coupled to the desired memory chip.

14 . The system according to claim 10 , wherein one of the plurality of chips is a logic chip, and
the logic chip is configured to set a chip ID thereof to an initial value, and transmit the chip ID set to the initial value or the external code as the chip code to an upper chip.

15 . The system according to claim 10 , wherein the plurality of chips comprise a logic chip and a plurality of memory chips stacked over the logic chip, and
each of the memory chips is configured to set a value obtained by adding a predetermined value to the chip code provided from a lower chip, as a chip ID thereof.

16 . The system according to claim 10 , wherein the plurality of chips comprise a logic chip and a plurality of memory chips stacked over the logic chip, and
each of the plurality of chips comprises: a plurality of through-chip vias; and an ID setup and test unit configured to set the chip ID of the chip using the chip code provided from a lower chip according to whether the current mode is a test mode, or perform the through-chip via test.

17 . The system according to claim 10 , wherein the plurality of chips comprise a logic chip and a plurality of memory chips stacked over the logic chip, and
each of the plurality of chips comprises: a plurality of through-chip vias; a current source coupled to the plurality of through-chip vias; an adder configured to add a predetermined value to the chip code; and a logic element configured to activate the current source when an output of the adder coincides with a target value.

18 . The system according to claim 17 , further comprising a comparator configured to compare an external code inputted in a normal mode to the output of the adder, and determine whether to select a chip.

Assignees

• Sk Hynix Inc

Inventors

• Kim Ji Hwan

Classifications

• G11C29/14

  Implementation of control logic, e.g. test mode decoders · CPC title

• G11C29/82 Primary

  for EEPROMs · CPC title

• G11C5/02

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title

• G11C2029/4002

  Comparison of products, i.e. test results of chips or with golden chip · CPC title

• G11C29/54

  Arrangements for designing test circuits, e.g. design for test [DFT] tools · CPC title