Goa circuit applied to liquid crystal display device

Patent metadata

Field	Value
Publication number	US-2016189648-A1
Application number	US-201514418087-A
Country	US
Kind code	A1
Filing date	Jan 8, 2015
Priority date	Dec 31, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

A GOA (Gate On Array) circuit applied to a liquid crystal display device is disclosed. The liquid crystal display device has a plurality of scan lines. The GOA circuit has a plurality of cascaded shift register units. An (N)th level shift register unit controls charge to an (N)th level scanning line. The (N)th level shift register unit includes a forward-rearward scan circuit, a pull-up circuit, an bootstrap capacitor circuit, a gate signal point electricity leakage preventing circuit, and a pull-down sustain circuit. The bootstrap capacitor circuit, the gate signal point electricity leakage preventing circuit, and the pull-down sustain circuit are connected together with each other to form a gate signal point, so as to raise the stability of the gate signal point and to decrease the use of switches.

First claim

What is claimed is:

1 . A GOA (Gate Driver on Array) circuit applied to a liquid crystal display device, the liquid display device comprising a plurality of scanning lines, the GOA circuit comprising a plurality of cascaded shift register units, wherein an (N)th level shift register unit controls charge to an (N)th level scanning line (G(N)), the (N)th level shift register unit comprises:
a pull-down sustain circuit ( 500 ) connected with the (N)th level scanning line (G(N)); a bootstrap capacitor circuit ( 300 ) connected with the pull-down sustain circuit ( 500 ); a gate signal point (Q) electricity leakage preventing circuit ( 400 ) connected with the bootstrap capacitor circuit ( 300 ); a forward-rearward scan circuit ( 100 ) connected with gate signal point (Q) electricity leakage preventing circuit ( 400 ); and a pull-up circuit ( 200 ) connected with the bootstrap capacitor circuit ( 300 ); wherein the bootstrap capacitor circuit ( 300 ), the gate signal point (Q) electricity leakage preventing circuit ( 400 ), and the pull-down sustain circuit ( 500 ) are connected together with each other to form a gate signal point (Q(N)); the pull-up circuit ( 200 ), the bootstrap capacitor circuit ( 300 ,) and the gate signal point (Q) electricity leakage preventing circuit ( 400 ) are respectively connected with the (N)th level scanning line (G(N)); the forward-rearward scan circuit ( 100 ) is respectively connected with an (N−1)th level scanning line (G(N−1)) and an (N+1)th level scanning line (G(N+1)); the pull-down sustain circuit ( 500 ) comprises:
a first switch (T 9 ) having a control terminal which is connected with the gate signal point (Q) electricity leakage preventing circuit ( 400 ), and having an output terminal connected with a first circuit point (P(N));
a second switch (T 8 ) having a control terminal which is connected with the gate signal point (Q(N), and having an output terminal connected with the first circuit point (P(N));
a third switch (T 7 ) having a control terminal which is connected with the first circuit point (P(N)), having an input terminal connected with a high constant voltage (VGH), and having an output terminal connected with the (N)th level scanning line (G(N));
a fourth switch (T 6 ) having a control terminal which is connected with the first circuit point (P(N)), and having an input terminal connected with the high constant voltage (VGH);
a fifth switch (T 5 ) having a control terminal receiving an (N)th level first clock signal (CK(N)), having an input terminal connected with an output of the fourth switch (T 6 ), and having an output terminal connected with the gate signal point (Q; and
a first capacitor (C 2 ) having two ends which are respectively connected with the high constant voltage (VGH) and the first circuit point (P(N));
the forward-rearward scan circuit ( 100 ) comprises:
a sixth switch (T 1 ) having a control terminal which receives an up-to-down control signal (U2D), an input terminal connected with the (N−1)th level scanning line (G(N−1)), and an output terminal connected with the gate signal point (Q) electricity leakage preventing circuit ( 400 );
a seventh switch (T 2 ) having a control terminal which receives a down-to-up control signal (D2U), an input terminal connected with the (N+1)th level scanning line (G(N+1)), and an output terminal connected with the output terminal of the fifth switch (T 1 ) and the gate signal point (Q) electricity leakage preventing circuit ( 400 );
the gate signal point (Q) electricity leakage preventing circuit ( 400 ) comprises:
a ninth switch (T 3 ) having a control terminal which is connected with an input terminal of the first switch (T 9 ) to receive an (N)th level second clock signal (XCK(N)), having an input terminal connected with the output terminal of the sixth switch (T 1 ) and the output terminal of the seventh switch (T 2 ), and having an output terminal connected with the gate signal point (Q(N));
the (N)th level second clock signal (XCK(N)) and the first clock signal (CK) are reverse signals with regard to each other;
the gate signal point (Q) electricity leakage preventing circuit ( 400 ) comprises:
a ninth switch (T 3 ) having a control terminal which is connected with an input terminal of the first switch (T 9 ) and a constant low voltage (VGL), and having an output terminal connected with the gate signal point (Q(N));
a tenth switch (T 10 ) having a control terminal which is connected with the control terminal of the first switch (T 9 ), having an input terminal connected with the output terminal of the sixth switch (T 1 ) and the output terminal of the seventh switch (T 2 ), and having an output terminal connected with the input terminal of the ninth switch (T 3 );
the bootstrap capacitor circuit ( 300 ) comprises:
a second capacitor (C 1 ) having two ends which are respectively connected with the gate signal point (Q(N)) and the (N)th level scanning line (G(N));
the pull-down control circuit ( 600 ) comprises:
an eleventh switch (T 11 ) having a control terminal which receives the up-to-down control signal (U2D), having an input terminal which receives a second positive clock signal (XCKF), and having an output terminal connected with the pull-down sustain circuit ( 500 ) and the gate signal point (Q) electricity leakage preventing circuit ( 400 );
a twelfth switch (T 12 ) having a control terminal which receives the down-to-up control signal (D2U), having an input terminal which receives a second reverse clock signal (XCKR), and having an output terminal connected with the pull-down sustain circuit ( 500 ) and the gate signal point (Q) electricity leakage preventing circuit ( 400 );
the output terminal of the eleventh switch (T 11 ), the output terminal of the twelfth switch (T 12 ), and the control terminal of the first switch (T 9 ) being connected with each other;
the pull-down sustain circuit ( 500 ) further comprises:
a thirteenth switch (T 13 ) having a control terminal which is connected with the gate signal point (Q), having an input terminal connected with the control terminal of the first switch (T 9 ), and having an output terminal connected with the first circuit point (P(N)).

2 . The GOA circuit applied to the liquid crystal display device according to claim 1 , wherein the pull-up circuit ( 200 ) comprises:
an eighth switch (T 4 ) having a control terminal which is connected with the gate signal point (Q(N)), having an input terminal connected with the (N)th level first clock signal (CK(N)), and having an output terminal connected with the (N)th level scanning line (G(N)).

3 . The GOA circuit applied to the liquid crystal display device according to claim 1 , wherein the pull-down sustain circuit ( 500 ) further comprises:
a fourteenth switch (T 14 ) having a control terminal which receives an (N−1)th level second clock signal (XCK(N−1)), having an input terminal connected with the output terminal of the fourth switch (T 6 ), and having an output terminal connected with the gate signal point (Q(N)).

4 . The GOA circuit applied to the liquid crystal display device according to claim 1 , wherein the pull-down sustain circuit ( 500 ) further comprises:
a fourteenth switch (T 14 ) having a control terminal which receives an (N−2)th level second clock signal (XCK(N−2)), having an input terminal connected with the output terminal of the fourth switch (T 6 ), and having an output terminal connected with the gate signal point (Q(N)).

5 . A GOA (Gate Driver on Array) circuit applied to a liquid crystal display device, the liquid display device comprising a plurality of scanning lines, the GOA circuit comprising a plurality of cascaded shift register units, wherein an (N)th level shift register unit controls charge to an (N)th level scanning line (G(N)), the (N

Assignees

• Shenzhen China Star Optoelect

Inventors

• Xiao Juncheng

Classifications

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3696

  Generation of voltages supplied to electrode drivers · CPC title