Gate driver, display device with the same and driving method thereof

Patent metadata

Field	Value
Publication number	US-2016189646-A1
Application number	US-201514971387-A
Country	US
Kind code	A1
Filing date	Dec 16, 2015
Priority date	Dec 31, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

A display device according to an embodiment includes a display panel in which a plurality of gate and date lines are formed, and a gate driver configured to include first and second shift registers and a control portion. The first shift register is disposed opposite to odd-numbered gate lines of the display panel. The second shift register is disposed opposite to even-numbered gate lines of the display panel. The control portion transfers a first control signal to the first shift register, derives a second control signal from the first control signal, and applies the second control signal to the second shift register.

First claim

What is claimed is:

1 . A gate driver comprising:
a shift register configured to include a first shift register opposite to odd-numbered gate lines of a display panel, and a second shift register opposite to even-numbered gate lines of the display panel; and a control portion configured to transfer a first control signal to the first shift register, derive a second control signal from the first control signal, and apply the second control signal to the second shift register.

2 . The gate driver of claim 1 , wherein the first control signal includes a gate start pulse and a gate shift clock.

3 . The gate driver of claim 1 , wherein the second control signal is obtained by delaying the first control signal.

4 . The gate driver of claim 3 , wherein the control portion includes:
a buffer unit configured to output the second control signal; and a counter unit configured to count a delay period of the first control signal.

5 . The gate driver of claim 1 , further comprising an output portion configured to output gate signals generated in the first and second shift registers.

6 . A display device comprising:
a display panel in which a plurality of gate lines and a plurality of data lines are formed, the plurality of gate lines including odd-numbered gate lines and even-numbered gate lines; and a gate driver which includes: a first shift register opposite to the odd-numbered gate lines of the display panel; a second shift register opposite to the even-numbered gate lines of the display panel; and a control portion configured to transfer a first control signal to the first shift register, derive a second control signal from the first control signal, and apply the second control signal to the second shift register.

7 . The display device of claim 6 , wherein the first control signal includes a gate start pulse and a gate shift clock.

8 . The display device of claim 6 , wherein the second control signal is obtained by delaying the first control signal.

9 . The display device of claim 8 , wherein the control portion includes:
a buffer unit configured to output the second control signal; and a counter unit configured to count a delay period of the first control signal.

10 . The display device of claim 6 , wherein the gate driver further includes an output portion configured to output gate signals generated in the first and second shift registers to the gate lines of the display panel.

11 . The display device of claim 6 , wherein the gate driver is disposed on the display panel through one of chip-on-glass and line-on-glass processes.

12 . A method of driving a display device which includes a display panel configured to include a plurality of gate lines and a plurality of data lines, and a gate driver configured to include a first shift register opposite to odd-numbered gate lines of a display panel, a second shift register opposite to even-numbered gate lines of the display panel and a control portion connected the first and second shift registers, the method comprising:
enabling the control portion to derive a second control signal from a first control signal; applying the first control signal to the first shift register and the second control signal to the second shift register; and transferring first gate signals from the first shift register and second gate signals from the second shift register to the odd-numbered and the even-numbered gate lines.

13 . The method of claim 12 , wherein the first control signal includes a gate start pulse and a gate shift clock.

14 . The method of claim 12 , wherein the second control signal is obtained by delaying the first control signal.

Assignees

• Lg Display Co Ltd

Inventors

• Hong Seok Hyun
• Lim Myung Gi
• Do O Sung

Classifications

• G09G3/3611 Primary

  Control of matrices with row and column drivers · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title