Methods for retargeting circuit design layouts and for fabricating semiconductor devices using retargeted layouts

Patent metadata

Field	Value
Publication number	US-2016188781-A1
Application number	US-201514699705-A
Country	US
Kind code	A1
Filing date	Apr 29, 2015
Priority date	Dec 29, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

Methods for retargeting a circuit design layout for a multiple patterning lithography process and for fabricating a semiconductor device are provided. In an exemplary embodiment, a computer-executed method for retargeting a circuit design layout for a multiple patterning lithography process is provided. The method includes decomposing a circuit design layout file to produce decomposed layout files in a computer. Each decomposed layout file is associated with a respective mask for use in the multiple patterning lithography process. The method includes preparing retargeted layout files in the computer by retargeting selected decomposed layout files based on photolithography limitations specific to each selected decomposed layout file to produce retargeted layout files. Also, the method includes determining in the computer that a combination of layout files includes a spacing conflict. The method further includes resolving the spacing conflict in the computer by modifying the layout file or layout files causing the spacing conflict.

First claim

What is claimed is:

1 . A computer-executed method for retargeting a circuit design layout for a multiple patterning lithography process, the method comprising:
decomposing a circuit design layout file to produce decomposed layout files in a computer, wherein each decomposed layout file is associated with a respective mask for use in the multiple patterning lithography process; retargeting selected decomposed layout files based on photolithography limitations specific to each selected decomposed layout file to produce retargeted layout files; determining in the computer that a combination of layout files includes a spacing conflict; and resolving the spacing conflict in the computer by modifying the layout file or layout files causing the spacing conflict.

2 . The computer-executed method of claim 1 wherein:
the circuit design layout file includes a pattern of features;
each decomposed layout file includes a feature; and
retargeting a first selected decomposed layout file comprises adjusting a width of a respective feature in the first selected decomposed layout file to form an adjusted feature.

3 . The computer-executed method of claim 2 wherein:
the first selected decomposed layout file includes a terminal feature and a non-terminal feature; and
retargeting the first selected decomposed layout file comprises making a greater adjustment to the width of the terminal feature than to the width of the non-terminal feature.

4 . The computer-executed method of claim 2 wherein:
the first selected decomposed layout file includes isolated features and non-isolated features; and
retargeting the first selected decomposed layout file comprises making a greater adjustment to the widths of the isolated features than to the widths of the non-isolated features.

5 . The computer-executed method of claim 2 wherein determining that the combination of layout files includes a spacing conflict comprises analyzing whether adjacent features in the combination of layout files violate a minimum spacing therebetween.

6 . The computer-executed method of claim 5 wherein resolving the spacing conflict comprises modifying the layout file or layout files causing the spacing conflict using equal violation retract.

7 . The computer-executed method of claim 5 wherein resolving the spacing conflict comprises modifying the layout file or layout files causing the spacing conflict using conflict resolution tables.

8 . A computer-executed method for retargeting a circuit design layout for a multiple patterning lithography process, the method comprising:
decomposing a circuit design layout file to produce decomposed layout files in a computer, wherein each decomposed layout file is associated with a respective mask for use in the multiple patterning lithography process, and wherein each decomposed layout file includes at least one feature; creating an estimated layout file in the computer for each decomposed layout file by estimating an adjustment for each feature therein based on a lithography process window of each feature relative to the respective decomposed layout file; and preparing retargeted layout files in the computer by retargeting each decomposed layout file based on the adjustments.

9 . The computer-executed method of claim 8 wherein creating an estimated layout file for each decomposed layout file comprises estimating a width adjustment for a selected feature.

10 . The computer-executed method of claim 8 wherein creating an estimated layout file for each decomposed layout file comprises estimating a location adjustment for a selected feature.

11 . The computer-executed method of claim 8 further comprising:
determining in the computer whether a combination of the estimated layout files includes spacing conflicts; and
resolving spacing conflicts in the computer by modifying selected adjustments.

12 . The computer-executed method of claim 11 wherein determining whether the combination of the estimated layout files includes spacing conflicts comprises analyzing whether adjacent features in the combination of the estimated layout files violate a minimum spacing therebetween.

13 . The computer-executed method of claim 12 wherein resolving the spacing conflicts comprises modifying the selected adjustments using equal violation retract.

14 . The computer-executed method of claim 12 wherein resolving the spacing conflicts comprises modifying the selected adjustments using conflict resolution tables.

15 . The computer-executed method of claim 8 wherein estimating the adjustment for each feature comprises estimating an adjustment to a width of a respective feature if the respective feature violates a respective photolithography limitation.

16 . The computer-executed method of claim 8 wherein:
a selected decomposed layout file includes a terminal feature and a non-terminal feature; and
creating the estimated layout file comprises estimating a greater adjustment for terminal feature than for the non-terminal feature.

17 . The computer-executed method of claim 8 wherein:
the decomposed layout files include isolated features and non-isolated features; and
creating the estimated layout file comprises estimating a greater adjustment for the isolated features than for the non-isolated features.

18 . A method for fabricating a semiconductor device, the method comprising:
decomposing a circuit design layout file to produce decomposed layout files; preparing retargeted layout files by retargeting each decomposed layout file based on photolithography limitations specific to each decomposed layout file; determining whether a combination of the retargeted layout files includes spacing conflicts; resolving the spacing conflicts by modifying selected retargeted layout files; fabricating a plurality of masks based on the retargeted layout files; and performing a multiple patterning lithography process with the plurality of masks on a semiconductor substrate.

19 . The method of claim 18 wherein:
each decomposed layout file includes at least one feature; and
retargeting each decomposed layout file comprises adjusting a width or location of a selected feature in each decomposed layout file.

20 . The method of claim 18 wherein:
each decomposed layout file includes at least one feature; and
determining whether the combination of the retargeted layout files includes spacing conflicts comprises analyzing whether adjacent features in the combination of the retargeted layout files violate a minimum spacing therebetween.

Assignees

• Globalfoundries Inc

Inventors

• Hamouda Ayman
• Kallingal Chidam
• Chen Norman

Classifications

• G03F1/36

  Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G03F1/70 Primary

  Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G06F17/5081 Primary

  Physics · mapped topic