Driving circuit, array substrate, touch display device, and driving method of the touch display device

Patent metadata

Field	Value
Publication number	US-2016188091-A1
Application number	US-201514968110-A
Country	US
Kind code	A1
Filing date	Dec 14, 2015
Priority date	Dec 31, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

A driving circuit, an array substrate, a touch display device and a driving method of the touch display device. The first gate driving circuits and the touch driving circuits electrically connected with the first gate driving circuits are disposed in the driving circuit, and the secondary trigger signals outputted from the shift registers of the first gate driving circuit function as the strobe signals of the touch selection outputting units from the touch driving circuits, respectively.

First claim

We claim:

1 . A driving circuit, comprising: a first gate driving circuit and a touch driving circuit, wherein,
the first gate driving circuit comprises N stages of shift registers electrically connected in series with each other, N is a positive integer larger than 1, wherein, each stage of shift register from the N stages of shift registers comprises a trigger signal inputting terminal and a secondary trigger signal outputting terminal; and for two adjacent stages of shift registers electrically connected in series from the N stages of shift registers, the secondary trigger signal outputting terminal of the preceding stage of shift register is electrically connected with the trigger signal inputting terminal of the next stage of shift register; the touch driving circuit comprises M stages of touch selection outputting units for generating touch driving signals, M is a positive integer smaller than or equal to N, each stage of touch selection outputting unit from the M stages of touch selection outputting units comprises a strobe signal inputting terminal; and the strobe signal inputting terminals of the stages of touch selection outputting units from the touch driving circuit are respectively electrically connected with the secondary trigger signal outputting terminals of the corresponding stages of shift registers from the first gate driving circuit.

2 . The driving circuit of claim 1 , wherein, each stage of touch selection outputting unit further comprises: a buffer subunit, a first signal transmitting subunit, a second signal transmitting subunit and a touch driving signal outputting terminal, wherein, the buffer subunit is configured to buffer the strobe signal received from the strobe signal inputting terminal;
the first signal transmitting subunit is configured to transmit a first signal according to the strobe signal buffered by the buffer subunit, and the first signal in turn is outputted from the touch driving signal outputting terminal; and the second signal transmitting subunit is configured to transmit a second signal according to the strobe signal buffered by the buffer subunit, and the second signal is in turn outputted from the touch driving signal outputting terminal.

3 . The driving circuit of claim 2 , wherein, the buffer subunit comprises L 1 first inverters comprising the first first inverter to the L 1 -th first inverter electrically connected in series with each other, an input terminal of the first first inverter is electrically connected with the strobe signal inputting terminal, and the L 1 -th first inverter is electrically connected with the first signal transmitting subunit and the second signal transmitting subunit, wherein, L 1 is a positive integer;
the first signal transmitting subunit comprises a first NMOS transistor, a first PMOS transistor and a first signal inputting terminal, wherein, if L 1 is an odd number, a gate electrode of the first NMOS transistor is electrically connected with an input terminal of the L 1 -th first inverter, and a gate electrode of the first PMOS transistor is electrically connected with an output terminal of the L 1 -th first inverter; if L 1 is an even number, the gate electrode of the first PMOS transistor is electrically connected with the input terminal of the L 1 -th first inverter, and the gate electrode of the first NMOS transistor is electrically connected with the output terminal of the L 1 -th first inverter; a source electrode of the first NMOS transistor and a drain electrode of the first PMOS transistor are electrically connected with each other and further electrically connect with the first signal inputting terminal, and a drain electrode of the first NMOS transistor and a source electrode of the first PMOS transistor are electrically connected with each other and further electrically connect with the touch driving signal outputting terminal; and
the second signal transmitting subunit comprises a second NMOS transistor, a second PMOS transistor and a second signal inputting terminal, wherein, if L 1 is an odd number, a gate electrode of the second PMOS transistor is electrically connected with an input terminal of the L 1 -th first inverter, and a gate electrode of the second NMOS transistor is electrically connected with an output terminal of the L 1 -th first inverter; if L 1 is an even number, the gate electrode of the second NMOS transistor is electrically connected with the input terminal of the L 1 -th first inverter, and the gate electrode of the second NMOS transistor is electrically connected with the output terminal of the L 1 -th first inverter; a source electrode of the second NMOS transistor and a drain electrode of the second PMOS are electrically connected with each other and further electrically connect with the second signal inputting terminal, and a drain electrode of the second NMOS transistor and a source electrode of the second PMOS transistor are electrically connected with each other and further electrically connect with the touch driving signal outputting terminal.

4 . The driving circuit of claim 1 , wherein, shift registers electrically connected with any two adjacent stages of the touch selection outputting units are spaced by the same number of stages of shift registers.

5 . The driving circuit of claim 1 wherein, each stage of shift register further comprises: a latch, an NAND gate, a second inverter, a third inverter, a fourth inverter, a first clock signal inputting terminal, a second clock signal inputting terminal, a reset signal inputting terminal, and a scanning signal outputting terminal;
a first input terminal of the latch is electrically connected with the first clock signal inputting terminal of the stage of shift register, a second input terminal of the latch is electrically connected with the trigger signal inputting terminal of the stage of shift register, a third input terminal of the latch is electrically connected with the reset signal inputting terminal of the stage of shift register, and an output terminal of the latch is electrically connected with the secondary trigger signal outputting terminal; and
a first input terminal of the NAND gate is electrically connected with the output terminal of the latch, a second input terminal of the NAND gate is electrically connected with the second clock signal inputting terminal, an output terminal of the NAND is electrically connected with an input terminal of the second inverter; the second inverter, the third inverter and the fourth inverter are electrically connected in series sequentially, and an output terminal of the fourth inverter is electrically connected with the scanning signal outputting terminal.

6 . An array substrate, comprising: a display region and a peripheral region surrounding the display region, wherein, the peripheral region comprises a first driving circuit disposed at one side of the peripheral region, wherein, the first driving circuit is a driving circuit comprising: a first gate driving circuit and a touch driving circuit, wherein,
the first gate driving circuit comprises N stages of shift registers electrically connected in series with each other, N is a positive integer larger than 1, wherein, each stage of shift register from the N stages of shift registers comprises a trigger signal inputting terminal and a secondary trigger signal outputting terminal; and for two adjacent stages of shift registers electrically connected in series from the N stages of shift registers, the secondary trigger signal outputting terminal of the preceding stage of shift register is electrically connected with the trigger signal inputting terminal of the next stage of shift register; the touch driving circuit comprises M stages of touch selection outputting units for generating touch driving signals, M is a positive

Assignees

• Xiamen Tianma Micro Electronics Co Ltd
• Tianma Micro Electronics Co Ltd

Inventors

• Sun Ying
• Xu Yumin

Classifications

• G06F3/0412

  Digitisers structurally integrated in a display · CPC title

• G06F3/0416 Primary

  Control or interface arrangements specially adapted for digitisers · CPC title

• G06F3/044

  by capacitive means · CPC title

• G06F3/0446 Primary

  using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes · CPC title

• G06F3/04166

  Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving (Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184) · CPC title