Reliability of physical unclonable function circuits

Patent metadata

Field	Value
Publication number	US-2016182045-A1
Application number	US-201414913285-A
Country	US
Kind code	A1
Filing date	Aug 21, 2014
Priority date	Aug 21, 2013
Publication date	Jun 23, 2016
Grant date	—

Abstract

Techniques and circuits are disclosed for obtaining a physical unclonable function (PUF) circuit that is configured to provide, during a first operational mode, an output signal that is dependent on an electric characteristic of the PUF circuit. Techniques and circuits described herein can cause the PUF circuit to enter a second operational mode by applying a stress signal to the PUF circuit that changes a value of the electric characteristic relative to another value of the electric characteristic during the first operational mode of the PUF circuit; and adjusting, based on changing the absolute value of the first electric characteristic, a bias magnitude of the output signal relative to another bias magnitude of the output signal during the first operational mode of the PUF circuit.

First claim

What is claimed is:

1 . A method comprising:
obtaining a physical unclonable function (PUF) circuit,
said PUF circuit configured to provide, during a first operational mode, an output signal that is dependent on an electric characteristic of the PUF circuit; and
causing the PUF circuit to enter a second operational mode by:
applying a stress signal to the PUF circuit that changes an absolute value of the electric characteristic, relative to another value of the electric characteristic during the first operational mode of the PUF circuit; and
adjusting, based on changing the absolute value of the electric characteristic, a bias magnitude of the output signal relative to another bias magnitude of the output signal during the first operational mode of the PUF circuit.

2 . The method of claim 1 , wherein, adjusting, based on changing the absolute value of the electric characteristic, the bias magnitude of the output signal comprises changing the bias magnitude of the output signal relative to a previous bias magnitude of the output signal before the application of the stress signal.

3 . The method of claim 1 , wherein, applying the stress signal to the PUF circuit that changes an absolute value of the electric characteristic comprises applying the stress signal to the PUF circuit to increase the absolute value of the electric characteristic.

4 . The method of claim 1 , wherein adjusting, based on changing the absolute value of the electric characteristic, the bias magnitude of the output signal comprises:
increasing a probability of the PUF circuit for resolving to a certain output value during a plurality of times the PUF circuit is operated in the first operational mode, relative to another probability of the PUF circuit resolving to the certain output value independent of the adjusting.

5 . The method of claim 1 , wherein causing the PUF circuit to enter the second operational mode comprises stressing the PUF circuit by a response reinforcement process to increase the value of the electric characteristic, relative to the other value of the electric characteristic during the first operational mode of the PUF circuit, wherein the response reinforcement process is based on a circuit aging phenomena.

6 . The method of claim 1 , wherein causing the PUF circuit to enter the second operational mode comprises:
stressing the PUF circuit by a response reinforcement process to increase the value of the electric characteristic, relative to the other value of the electric characteristic during the first operational mode of the PUF circuit, wherein the response reinforcement process is selected one or more of a) hot carrier injection, b) negative-bias temperature instability, c) positive-bias temperature instability, and d) electromigration.

7 . The method of claim 1 , further comprising:
restoring the PUF circuit to the first operational mode, following a certain duration of the stress signal; and exiting the second operational mode.

8 . The method of claim 1 , wherein the PUF circuit comprises a delay based PUF circuit.

9 . The method of claim 1 , wherein the PUF circuit comprises a bistable based PUF circuit.

10 . The method of claim 1 , wherein obtaining the PUF circuit comprises:
obtaining a substrate that comprises the PUF circuit; wherein the output signal is further dependent on one or more physical characteristics of the substrate.

11 . The method of claim 1 , wherein the electric characteristic comprises a first electric characteristic, and wherein the method further comprises:
causing each of a first input and a second input of the PUF circuit to be set to a predetermined voltage level; wherein the First and second inputs of the PUF circuit are respectively connected to at least a first circuit component having the electric characteristic as a first electric characteristic and a second circuit component having a second, different electric characteristic; and receiving the output signal of the PUF circuit, wherein the output signal is based on the first and second electric characteristics.

12 . The method of claim 11 , wherein the first and second circuit components comprise first and second transistor devices, respectively, and the first and second electric characteristics comprise first and second threshold voltages, respectively, for the corresponding first and second transistor devices.

13 . The method of claim 11 , wherein the output signal is based on a difference between a first and a second delay value for the corresponding first and second circuit components.

14 . The method of claim 12 , wherein the output signal is based on a difference in magnitudes between the first and second threshold voltages.

15 . The method of claim 11 , further comprising:
during the second operational mode: applying the stress signal as a first stress signal to a first one of the first and second transistor devices; and applying a second, different stress signal to a second, different one of the first and second transistor devices.

16 . The method of claim 11 , further comprising:
during the first operational mode, storing first and second transistor device output values that are based on the bias magnitude of the output signal; based on the first and second transistor device output values, determining which of the first and second transistors devices is to be stressed; during the second operational mode, selecting one of the first and second transistor devices to be stressed, based on the stored first and second transistor device output values; and applying the stress signal to the selected one of the first and second transistor devices.

17 . The method of claim 1 , wherein the stress signal comprises a stress voltage signal with a stress magnitude that is greater than a voltage magnitude of an operating voltage used during the first operational mode of the PUF circuit.

18 . The method of claim 17 , wherein the stress magnitude is at least 1.25 times the voltage magnitude of the operating voltage used during the first operational mode of the PUF circuit.

19 . The method of claim 1 , wherein the stress signal comprises a stress circuit signal with a magnitude that is greater than a current magnitude of a current flowing during the first operational mode of the PUF circuit.

20 . The method of claim 1 , further comprising:
selecting at least one of a magnitude and a duration of the stress signal, with selecting based on a magnitude of a stress signal value and a duration of the stress signal value for causing at least plurality of carriers in a first transistor device of the PUF circuit to be injected into a gate oxide of the first transistor device.

21 . The method of claim 1 , wherein applying the stress signal to the PUF circuit comprises:
causing a stress current with a stress current magnitude that is greater than an operating current magnitude of an operating current that is flowing during the first operational mode; wherein a flow of the stress current during the second operational mode is in a same direction as a flow of the operating current during the first operational mode.

22 . The method of claim 1 , wherein adjusting, based on changing the absolute value of the electric characteristic, the bias magnitude of the output signal comprises:
increasing a probability of the PUF circuit for resolving to a certain output value over a plurality of operating conditions, relative to another probability of the PUF circ

Assignees

• Univ Carnegie Mellon

Inventors

• Mai Kenneth Wei-An
• Bhargava Mudit

Classifications

• H04L9/0866

  involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics · CPC title

• G09C1/00

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

• H04L9/3278

  using physically unclonable functions [PUF] · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title

• H03K19/00315 Primary

  in field-effect transistor circuits · CPC title