Implementing adaptive control for optimization of pulsed resonant drivers

Patent metadata

Field	Value
Publication number	US-2016182016-A1
Application number	US-201414576517-A
Country	US
Kind code	A1
Filing date	Dec 19, 2014
Priority date	Dec 19, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

A method and circuit are provided for implementing adaptive control for optimization of pulsed resonant drivers, and a design structure on which the subject circuit resides. Peak detectors are used to detect a positive or up level reached by a resonant clock and negative or down level reached by the resonant clock. Each detected levels is compared to a reference level to determine when to vary the turn off timing of a clock driver pull-up device and/or a clock driver pull-down device. A positive peak detector controls the turn off time of the pull-up device and a negative peak detector controls a turn off time of the pull-down device in the pulsed resonant driver.

First claim

1 - 5 . (canceled)

6 . A circuit for implementing adaptive control for optimization of pulsed resonant drivers comprising:
a peak detector to detect a positive or up level reached by a resonant clock and negative or down level reached by the resonant clock; an analog compare and control coupled to said peak detector for comparing the detected levels to reference levels to determine when to vary the turn off timing of a clock driver pull-up device and a clock driver pull-down device; a pulsed driver coupled to said analog compare and control receiving control feedback signals for providing an adjusted timing control to the clock driver pull-up device and the clock driver pull-down device.

7 . The circuit as recited in claim 6 includes a variable voltage source coupled to said analog compare and control, said variable voltage source applying a positive reference level and a negative reference level.

8 . The circuit as recited in claim 7 includes said variable voltage source changing the reference level applied to said analog compare and control to control a resonant clock swing level relative to a voltage supply rail.

9 . The circuit as recited in claim 6 includes a first variable delay coupled to the clock driver pull-up device and a second variable delay coupled to the clock driver pull-down device, and wherein said analog compare and control providing a pull-up control feedback signal to the first variable delay and a pull-down control feedback signal to the second variable delay.

10 . The circuit as recited in claim 9 wherein said clock driver pull-up device comprises a P-channel field effect transistor (PFET) and said clock driver pull-down device comprises an N-channel field effect transistor (NFET).

11 . The circuit as recited in claim 10 wherein said clock driver pull-up PFET and said clock driver pull-down NFET connected in series between a voltage supply rail and ground.

12 . The circuit as recited in claim 11 wherein said first variable delay coupled to the clock driver pull-up PFET includes an OR gate receiving a clock input and an output coupled from said first variable delay and providing a gate input to the clock driver pull-up PFET.

13 . The circuit as recited in claim 6 wherein said second variable delay coupled to the clock driver pull-down NFET includes an AND gate receiving a clock input and an output coupled from said second variable delay and providing a gate input to the clock driver pull-down NFET.

14 . A design structure embodied in a non-transitory machine readable medium used in a design process, the design structure comprising:
a circuit tangibly embodied in the non-transitory machine readable medium used in the design process, said circuit for implementing adaptive control for optimization of pulsed resonant drivers said circuit comprising: a peak detector to detect a positive or up level reached by a resonant clock and negative or down level reached by the resonant clock; an analog compare and control coupled to said peak detector for comparing the detected levels to reference levels to determine when to vary the turn off timing of a clock driver pull-up device and a clock driver pull-down device; a pulsed driver coupled to said analog compare and control receiving control feedback signals for providing an adjusted timing control to the clock driver pull-up device and the clock driver pull-down device, wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said circuit.

15 . The design structure of claim 14 , wherein the design structure comprises a netlist, which describes said circuit.

16 . The design structure of claim 14 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

17 . The design structure of claim 14 , wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.

18 . The design structure of claim 14 , includes a variable voltage source coupled to said analog compare and control, said variable voltage source applying a positive reference level and a negative reference level, and said variable voltage source changing the reference level applied to said analog compare and control to control a resonant clock swing level relative to a voltage supply rail.

19 . The design structure of claim 14 , includes a first variable delay coupled to the clock driver pull-up device and a second variable delay coupled to the clock driver pull-down device, and wherein said analog compare and control providing a pull-up control feedback to the first variable delay and a pull-down control feedback to the second variable delay.

20 . The design structure of claim 14 , wherein said clock driver pull-up device comprises a P-channel field effect transistor (PFET) and said clock driver pull-down device comprises a N-channel field effect transistor (NFET).

Assignees

• IBM

Inventors

• Lukes Eric J
• Rosno Patrick L
• Schmerbeck Timothy J
• Yilma Dereje G

Classifications

• H03K3/012 Primary

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H03K19/0019 Primary

  by energy recovery or adiabatic operation · CPC title