Compensation circuit and inverter stage for oscillator circuit

Patent metadata

Field	Value
Publication number	US-2016181978-A1
Application number	US-201414576535-A
Country	US
Kind code	A1
Filing date	Dec 19, 2014
Priority date	Dec 19, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

A circuit includes an oscillator circuit to receive a bias current and generate an oscillating signal at an output node. A current differencing circuit subtracts a current at the output node from a reference current to generate a first current. In addition, a current mirroring circuit mirrors the first current to generate the bias current. An inverter stage is coupled to the output node, and includes an input branch configured to receive the oscillating signal and generate first and second control signals based upon the oscillating signal. At least one amplifying branch receives the first and second control signals and amplifies the first and second control signals. An output branch receives the amplified first and second control signals and generates an amplified version of the oscillating signal based upon the amplified first and second control signals.

First claim

1 . An electronic device, comprising:
an oscillator circuit having a motional resistance and a negative resistance, and comprising a crystal coupled to a first transistor; and a compensation circuit coupled to the oscillator circuit and configured to modulate a first current of the first transistor such that a transconductance of the first transistor increases the negative resistance in the oscillator circuit to compensate for the motional resistance in the oscillator circuit; wherein the compensation circuit comprises:
a second transistor having a first conduction terminal coupled to a node, a second conduction terminal coupled to a first reference supply voltage, and a control terminal coupled to the first transistor such that a second current flowing through the second transistor mirrors the first current;
a reference transistor having a first conduction terminal coupled to a second reference supply voltage, a second conduction terminal coupled to said node, and a control terminal coupled to receive a bias voltage that biases the reference transistor to generate a reference current applied to said node; and
a third transistor having a first conduction terminal coupled to said node, a second conduction terminal coupled to the second reference supply voltage, and a control terminal for controlling generation of said first current, the third transistor configured to carry a third current representing a difference between the reference current and the second current.

2 . The electronic device of claim 1 , wherein the first transistor of the oscillator circuit has a first conduction terminal coupled to the compensation circuit, and a second conduction terminal coupled to the second reference supply voltage; and wherein the compensation circuit is configured to modulate the first current flowing from the compensation circuit into the first conduction terminal of the first transistor of the oscillator circuit.

3 . The electronic device of claim 1 , wherein the oscillator circuit further comprises a first node and a second node; wherein the first transistor of the oscillator circuit has first conduction terminal coupled to the second node, a second conduction terminal coupled to the second reference supply voltage, and a control terminal coupled to the first node.

4 . (canceled)

5 . The electronic device of claim 1 , wherein the compensation circuit further comprises:
a fourth transistor having a first conduction terminal, a second conduction terminal coupled to the second reference supply voltage, and a control terminal coupled to the control terminal of the third transistor, the fourth transistor configured to mirror said third current; a fifth transistor having a first conduction terminal coupled to the first reference supply voltage, a second conduction terminal coupled to the fourth transistor, and a control terminal coupled to the fourth transistor, the fifth transistor configured to mirror the current in the fourth transistor; and a sixth transistor having a first conduction terminal coupled to the first reference supply voltage, a second conduction terminal coupled to the first transistor, and a control terminal coupled to the fifth transistor, the sixth transistor configured to mirror the current in the fifth transistor to generate said first current.

6 . The electronic device of claim 5 , further comprising a transient control circuit configured to limit current flow through the fifth transistor and the sixth transistor.

7 . The electronic device of claim 6 , wherein the transient control circuit comprises:
a seventh transistor having a first conduction terminal, a second conduction terminal coupled to the second reference supply voltage, and a control terminal coupled to the control terminal of the third transistor, the seventh transistor configured to mirror said third current; an eighth transistor having a first conduction terminal coupled to the first reference supply voltage, a second conduction terminal coupled to the seventh transistor, and a control terminal coupled to receive said bias voltage, the eighth transistor configured to generate a constant current; a ninth transistor having a first conduction terminal coupled to the first reference supply voltage, a second conduction terminal coupled to the seventh transistor, and a control terminal coupled to the seventh transistor, the ninth transistor configured to generate a difference current representing a difference between the mirror of the third current and the constant current; a tenth transistor having a first conduction terminal coupled to the first reference supply voltage, a second conduction terminal coupled to the fourth transistor, and a control terminal coupled to the ninth transistor, the tenth transistor configured to mirror said difference current for application to the fourth transistor, thereby limiting current flow through the fifth transistor.

8 . An electronic device, comprising:
an oscillator circuit comprising first and second nodes, and a crystal coupled to a first transistor having a first conduction terminal coupled to the second node, a second conduction terminal coupled to a second voltage, and a control terminal coupled to the first node; and a compensation circuit coupled to the oscillator circuit and configured to modulate a bias of the first transistor such that a transconductance of the first transistor compensates the oscillator circuit; wherein the first conduction terminal of the first transistor is coupled to the compensation circuit to receive a bias current; wherein the compensation circuit comprises:
a current reference node;
a third node;
a second transistor having a first conduction terminal coupled to the third node, a second conduction terminal coupled to the second voltage, and a control terminal coupled to the first node;
a reference transistor having a first conduction terminal coupled to a first voltage, a second conduction terminal coupled to the third node, and a control terminal coupled to the current reference node; and
a third transistor having a first conduction terminal coupled to the third node, a second conduction terminal coupled to the second voltage, and a control terminal.

9 . (canceled)

10 . (canceled)

11 . The electronic device of claim 8 , wherein the compensation circuit further comprises:
a fourth node coupled to the control terminal of the third transistor; a fifth node; a fourth transistor having a first conduction terminal coupled to the fifth node, a second conduction terminal coupled to the second voltage, and a control terminal coupled to the fourth node; a fifth transistor having a first conduction terminal coupled to the first voltage, a second conduction terminal coupled to the fifth node, and a control terminal coupled to the fifth node; and a sixth transistor having a first conduction terminal coupled to the first voltage, a second conduction terminal coupled to the second node, and a control terminal coupled to the fifth node.

12 . (canceled)

13 . (canceled)

14 . An inverter stage, comprising:
an input branch configured to receive an oscillating signal and to generate first and second control signals based upon the oscillating signal, the first and second control signals being offset by a threshold voltage; at least one amplifying branch configured to receive the first and second control signals and to amplify the first and second control signals; and an output branch configured to receive the amplified first and second control signals and to generate an amplified version of the oscillating signal based upon the amplified first and second control signals.

Assignees

• St Microelectronics Int Nv

Inventors

• Mittal Gauri
• Chatterjee Kallol
• Muktesh Pallavi
• Jain Nitin
• Badrathwal Pradeep Kumar

Classifications

• H03B5/366

  and comprising means for varying the frequency by a variable voltage or current · CPC title

• H03B5/364 Primary

  the amplifier comprising field effect transistors (H03B5/366 takes precedence) · CPC title

• H03B2200/0012

  Pierce oscillator · CPC title

• H03B2200/0038

  including a current mirror · CPC title