Card edge connectors

US2016181712A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016181712-A1
Application numberUS-201414575318-A
CountryUS
Kind codeA1
Filing dateDec 18, 2014
Priority dateDec 18, 2014
Publication dateJun 23, 2016
Grant date

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Techniques for manufacturing an add-in card are described. An example of an add-in card in accordance with the described techniques includes a circuit board with contact fingers formed on an outer surface of the circuit board. Each of the contact fingers is configured to make electrical contact with a pin when inserted into a receptacle. The gap between the contact fingers is greater than or equal to a width of the pin. The add-in card also includes a protection mechanism to prevent the pin from being captured between the contact fingers if the add-in card is misaligned when inserted or removed.

First claim

Opening claim text (preview).

What is claimed is: 1 . An add-in card, comprising: a circuit board; contact fingers disposed on an outer surface of the circuit board, each of the contact fingers to make electrical contact with a pin when inserted into a receptacle, wherein a gap between the contact fingers is greater than or equal to a width of the pin; and a protection mechanism to prevent the pin from being captured between the contact fingers if the add-in card is misaligned when inserted or removed. 2 . The add-in card of claim 1 , wherein the protection mechanism is a support step disposed between each of the contact fingers. 3 . The add-in card of claim 2 , wherein the support step comprises a plurality of support step segments that are electrically isolated from one another. 4 . The add-in card of claim 2 , wherein the support step is a raised metal pad that is electrically isolated from each of the contact fingers. 5 . The add-in card of claim 2 , wherein a gap between an edge of the support step and an edge of a nearest contact finger is less than a width of the pin. 6 . The add-in card of claim 2 , wherein the support step is disposed between a bottom end of the contact finger and a point at which the pin is to make contact the contact finger when fully inserted. 7 . The add-in card of claim 1 , wherein each of the contact fingers comprises a first portion with a first width and a second portion with a second width less than the first width, wherein the second portion is disposed below a point at which the pin is to make contact when fully inserted. 8 . The add-in card of claim 1 , wherein the add-in card is compliant with a PCIe Card Electromechanical Specification and a width of the contact fingers is less than or equal to 0.7 mm. 9 . The add-in card of claim 1 , wherein the add-in card is compliant with a PCIe Card Electromechanical Specification. 10 . A computing device, comprising: a baseboard comprising a receptacle for receiving an add-in card, the receptacle including pins; an add-in card inserted into the receptacle, the add-in card comprising a circuit board and contact fingers disposed on an outer surface of the circuit board to make contact with the pins; and a protection mechanism to prevent the pins from being captured between the contact fingers when inserted or removed. 11 . The computing device of claim 10 , wherein the protection mechanism is a support step disposed between each of the contact fingers. 12 . The computing device of claim 11 , wherein the support step comprises a plurality of support step segments that are electrically isolated from one another. 13 . The computing device of claim 11 , wherein the support step is a raised metal pad that is electrically isolated from each of the contact fingers. 14 . The computing device of claim 11 , wherein a gap between an edge of the support step and an edge of a nearest contact finger is less than a width of the pin. 15 . The computing device of claim 11 , wherein the support step is disposed between a bottom end of the contact finger and a point at which the pin is to contact the contact finger when fully inserted. 16 . The computing device of claim 10 , wherein each of the contact fingers comprises a first portion with a first width and a second portion with a second width less than the first width, wherein the second portion is disposed below a point at which the pin is to make contact the contact finger when fully inserted. 17 . The computing device of claim 10 , wherein the add-in card is compliant with a PCIe Card Electromechanical Specification and a width of the contact fingers is less than 0.7 mm. 18 . The computing device of claim 10 , wherein the protection mechanism is a widening of the pins at a point where the pins makes contact with the contact fingers. 19 . A method of manufacturing an electronic device, comprising: forming contact fingers on an outer surface of a circuit board, each of the contact fingers to make electrical contact with a pin when inserted into a receptacle, wherein a gap between the contact fingers is greater than or equal to a width of the pin; and forming a protection mechanism on a surface of the circuit board between the contact fingers to prevent damage to the pins and contact fingers during insertion and removal. 20 . The method of claim 19 , wherein forming the protection mechanism comprises forming metal pads between the contact fingers and electrically isolating the metals pads from the contact fingers. 21 . The method of claim 20 , wherein forming the contact fingers and forming the metal pads comprises a same metal patterning step. 22 . The method of claim 20 , wherein forming the metal pads comprises forming each of the metal pads in a plurality of electrically isolated segments. 23 . The method of claim 19 , wherein forming the contact fingers comprises forming a first portion with a first width and forming a second portion with a second width less than the first width, wherein the second portion is positioned below a point at which the pin is to make contact with the contact finger when fully inserted. 24 . A method of manufacturing an electronic device, comprising: forming a pin comprising a contact point to make contact with one of a plurality of contact fingers of an add-in card; and disposing the pin within a receptacle to receive the add-in card; wherein forming the pin comprises forming a protection mechanism that prevents the pin from being captured between the contact fingers. 25 . The method of claim 24 , wherein forming the protection mechanism comprises forming a widened portion at the contact point of the pin.

Assignees

Inventors

Classifications

  • with a panel or printed circuit board · CPC title

  • H01R12/721Primary

    cooperating directly with the edge of the rigid printed circuits · CPC title

  • Guiding, mounting, polarizing or locking means; Extractors (for printed circuit boards H05K) · CPC title

  • Printed circuits being substantially perpendicular to each other (for printed connections H05K3/366) · CPC title

  • Pads along the edge of rigid circuit boards, e.g. for pluggable connectors · CPC title

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What does patent US2016181712A1 cover?
Techniques for manufacturing an add-in card are described. An example of an add-in card in accordance with the described techniques includes a circuit board with contact fingers formed on an outer surface of the circuit board. Each of the contact fingers is configured to make electrical contact with a pin when inserted into a receptacle. The gap between the contact fingers is greater than or eq…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H01R12/721. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jun 23 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).