Electronic device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-2016181520-A1
Application number	US-201514846761-A
Country	US
Kind code	A1
Filing date	Sep 5, 2015
Priority date	Dec 17, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a substrate; a variable resistance element formed over the substrate; a top electrode formed over the variable resistance element; a barrier layer formed over the top electrode and including a groove; an interlayer dielectric layer formed over the substrate to have a layer structure in which the variable resistance element, the top electrode and the barrier layer are formed in the interlayer dielectric layer; and a metal wiring including a portion formed in the groove of the barrier layer.

First claim

What is claimed is:

1 . An electronic device comprising a semiconductor memory,
wherein the semiconductor memory comprises: a substrate; a variable resistance element formed over the substrate; a top electrode formed over the variable resistance element; a barrier layer formed over the top electrode and including a groove; an interlayer dielectric layer formed over the substrate to have a layer structure in which the variable resistance element, the top electrode and the barrier layer are formed in the interlayer dielectric layer; and a metal wiring including a portion formed in the groove of the barrier layer.

2 . The electronic device of claim 1 , wherein the barrier layer surrounds a part of the sidewall and the bottom of the metal wiring.

3 . The electronic device of claim 1 , wherein:
the metal wiring, in addition to the portion formed in the groove of the barrier layer, includes a second portion formed over the interlayer dielectric layer, and the barrier layer includes an extension protruding above the interlayer dielectric layer to surround sidewalls of the second portion of the metal wiring.

4 . The electronic device of claim 1 , wherein the barrier layer comprises a metal layer.

5 . The electronic device of claim 1 , wherein the barrier layer comprises tantalum, and the metal wiring comprises copper.

6 . The electronic device of claim 1 , wherein the metal wiring, in addition to the portion formed in the groove of the barrier layer, includes a second portion formed over the interlayer dielectric layer, and
the device further includes an insulating layer in which the second portion of the metal wiring is formed.

7 . The electronic device of claim 1 , further comprising an insulating layer formed over the interlayer dielectric layer and having an air gap around the metal wiring.

8 . The electronic device of claim 1 , further comprising a bottom electrode contact between the substrate and the variable resistance element.

9 . The electronic device of claim 1 , further comprising:
a source line contact formed in the interlayer dielectric layer to be adjacent to the variable resistance element and the top electrode; another barrier layer formed in the interlayer dielectric layer over the source line contact, and having a groove; and another metal wiring including a portion formed in the groove of another barrier layer and including another portion formed over the interlayer dielectric layer.

10 . The electronic device according to claim 1 , further comprising a microprocessor which includes:
a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor; an operation unit configured to perform an operation based on a result that the control unit decodes the command; and a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed, wherein the semiconductor memory unit that includes the resistance variable element is part of the memory unit in the microprocessor.

11 . The electronic device according to claim 1 , further comprising a processor which includes:
a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data; a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit, wherein the semiconductor memory unit that includes the resistance variable element is part of the cache memory unit in the processor.

12 . The electronic device according to claim 1 , further comprising a processing system which includes:
a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command; an auxiliary memory device configured to store a program for decoding the command and the information; a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside, wherein the semiconductor memory unit that includes the resistance variable element is part of the auxiliary memory device or the main memory device in the processing system.

13 . The electronic device according to claim 1 , further comprising a data storage system which includes:
a storage device configured to store data and conserve stored data regardless of power supply; a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside; a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside, wherein the semiconductor memory unit that includes the resistance variable element is part of the storage device or the temporary storage device in the data storage system.

14 . The electronic device according to claim 1 , further comprising a memory system which includes:
a memory configured to store data and conserve stored data regardless of power supply; a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside; a buffer memory configured to buffer data exchanged between the memory and the outside; and an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside, wherein the semiconductor memory unit that includes the resistance variable element is part of the memory or the buffer memory in the memory system.

15 . A method for fabricating an electronic device including a semiconductor memory, comprising:
forming a variable resistance element over a substrate; burying a first interlayer dielectric layer between the variable resistance elements; burying a top electrode contact in a part of a contact hole formed through the first interlayer dielectric layer, such that the top electrode contact is in contact with the variable resistance element; forming a mold layer over the top electrode contact and the first interlayer dielectric layer; etching the mold layer to form a damascene structure; burying a metal wiring in the damascene structure; etching the mold layer to form a barrier layer on the sidewall and bottom of the metal wiring; and burying a second interlayer dielectric layer between the metal wirings.

16 . A method for fabricating an electronic device including a semiconductor memory, comprising:
forming a first interlayer dielectric layer over a substrate, the first interlayer dielectric layer including a bottom electrode contact; forming a variable resistance element over the first interlayer dielectric layer such that the variabl

Assignees

• Sk Hynix Inc

Inventors

• Park Ju-Bong

Classifications

• G06F12/0802

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F2212/222

  Non-volatile memory · CPC title

• G06F2212/202

  Non-volatile memory · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title