Semiconductor Devices Having Buried Contact Structures and Methods of Manufacturing the Same

Patent metadata

Field	Value
Publication number	US-2016181385-A1
Application number	US-201514962003-A
Country	US
Kind code	A1
Filing date	Dec 8, 2015
Priority date	Dec 17, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

Semiconductor devices are provided including a substrate defining a gate trench. A buried gate structure is provided in the gate trench and at least fills the gate trench. The buried gate structure includes a gate insulation layer pattern, a gate electrode and a capping layer pattern. First and second impurity regions are provided at portions of the substrate adjacent to the buried gate structure, respectively. At least a portion of each of the first and second impurity regions face a sidewall of the buried gate structure. First and second buried contact structures are provided on the first and second impurity regions, respectively. Each of the first and second buried contact structures includes a metal silicide pattern and a metal pattern, and at least a portion of each of the first and second buried contact structures face to a sidewall of the buried gate structure.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate defining a gate trench therein; a buried gate structure in the gate trench and at least filling the gate trench to a top portion thereof, the buried gate structure including a gate insulation layer pattern, a gate electrode and a capping layer pattern; first and second impurity regions at portions of the substrate adjacent to the buried gate structure, respectively, at least a portion of each of the first and second impurity regions facing a sidewall of the buried gate structure; and first and second buried contact structures on the first and second impurity regions, respectively, each of the first and second buried contact structures including a metal silicide pattern and a metal pattern, and at least a portion of each of the first and second buried contact structures facing a sidewall of the buried gate structure.

2 . The semiconductor device of claim 1 , wherein the buried gate structure protrudes from a top portion of the gate trench.

3 . The semiconductor device of claim 1 , wherein top surfaces of the first and second impurity regions are lower than top portions of the gate electrode.

4 . The semiconductor device of claim 1 , wherein bottoms of the first and second impurity regions are lower than a central portion of the gate electrode corresponding to about ½ of a height of the gate electrode.

5 . The semiconductor device of claim 1 , wherein top surfaces of the first and second buried contact structures are substantially coplanar with that of the buried gate structure.

6 . The semiconductor device of claim 1 , wherein the metal silicide pattern directly contacts each of the first and second impurity regions.

7 . The semiconductor device of claim 1 , wherein a bottom of the metal silicide pattern is lower than a top surface of the gate electrode.

8 . The semiconductor device of claim 1 , wherein the metal silicide pattern includes at least one selected from the group consisting of cobalt silicide, nickel silicide, titanium silicide, tantalum silicide, molybdenum silicide, and tungsten silicide.

9 . The semiconductor device of claim 1 , further comprising an isolation layer on the substrate, wherein a top surface of the isolation layer is substantially coplanar with top surfaces of the first and second buried contact structures.

10 . The semiconductor device of claim 1 , further comprising:
a first contact plug on the first buried contact structure; a second contact plug on the second buried contact structure; a bit line electrically connected to the first contact plug; and a capacitor on the second contact plug.

11 . The semiconductor device of claim 1 , further comprising:
a source line on the first buried contact structure; a contact plug on the second buried contact structure; a variable resistance structure electrically connected to the contact plug; and a bit line on the variable resistance structure.

12 . A method of manufacturing a semiconductor device, the method comprising:
etching an upper portion of a substrate to form a gate trench therein; forming a buried gate structure in the gate trench such that the buried gate structure at least fills the gate trench, the buried gate structure including a gate insulation layer pattern, a gate electrode and a capping layer pattern; forming first and second impurity regions at portions of the substrate adjacent to the buried gate structure, respectively, at least a portion of each of the first and second impurity regions facing a sidewall of the buried gate structure; and forming first and second buried contact structures on the first and second impurity regions, respectively, each of the first and second buried contact structures including a metal silicide pattern and a metal pattern, and at least a portion of each of the first and second buried contact structures facing a sidewall of the buried gate structure.

13 . The method of claim 12 , wherein forming the buried gate structure comprises forming the buried gate structure to protrude from a top portion of the gate trench.

14 . The method of claim 12 , wherein forming the buried gate structure further comprises partially etching a portion of the substrate adjacent to the sidewall of the buried gate structure to form a recess having a bottom lower than a top surface of the gate electrode.

15 . The method of claim 12 , further comprising,
forming a first contact plug on the first buried contact structure; forming a second contact plug on the second buried contact structure; forming a bit line to be electrically connected to the first contact plug; and forming a capacitor on the second contact plug.

16 . The method of claim 15 :
wherein forming the first buried contact structure and the first contact plug comprises performing a first deposition process; and wherein forming the second buried contact structure and the second contact plug comprises performing a second deposition process.

17 . The method of claim 12 , further comprising,
forming a source line on the first buried contact structure; forming a contact plug on the second buried contact structure; forming a variable resistance structure to be electrically connected to the contact plug; and forming a bit line on the variable resistance structure.

18 . A method of forming a semiconductor device, the method comprising:
forming a buried gate structure in a gate trench defined by a substrate; forming first and second impurity regions spaced apart by the buried gate structure; and forming first and second buried contact structures on the first and second impurity regions, respectively, each of the first and second buried contact structures including a metal silicide pattern and a metal pattern, such that a portion of the substrate adjacent the first and second impurity regions is replaced with the metal pattern.

19 . The method of claim 18 , wherein forming the first and second buried contact structures comprising forming the first and second buried contact structures having top surfaces that are substantially coplanar with a top surface of the buried gate structure.

20 . The method of claim 18 , wherein metal silicide patterns of the first and second contact structures directly contact the first and second impurity regions, respectively.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Yong-Jun
• Kim Sung-In
• Song Jung-Woo
• Kahng Jae-Rok
• Kim Dae-Won

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/021

  of interconnections within wafers or substrates · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D64/027

  by etching at gate locations · CPC title