Making a flat no-lead package with exposed electroplated side lead surfaces

Patent metadata

Field	Value
Publication number	US-2016181122-A1
Application number	US-201414581233-A
Country	US
Kind code	A1
Filing date	Dec 23, 2014
Priority date	Dec 23, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

A method of making Flat No-Lead Packages with plated lead surfaces exposed on lateral faces thereof. The method includes providing a plurality of Flat No-Lead Packages having severed, unplated lead surfaces exposed on lateral faces thereof and having plated lead surfaces exposed on bottom faces thereof. The method further includes batch electroplating the severed unplated lead surfaces of the plurality of Flat No-Lead Packages.

First claim

1 . A method of making Flat No-Lead Packages with plated lead surfaces exposed on lateral sidewall surfaces of said Flat No-Lead Packages comprising:
providing a plurality of Flat No-Lead Packages having severed, unplated lead surfaces exposed on lateral faces thereof and having plated lead surfaces exposed on bottom faces thereof; and batch electroplating the severed unplated lead surfaces of the plurality of Flat No-Lead Packages.

2 . The method of claim 1 wherein said electroplating the severed unplated lead surfaces comprises:
electrically connecting a conductive strip to the plated lead portions of the plurality of Flat No-Lead Packages;
placing the Flat No-Lead Packages and the connected conductor strip in an electroplating bath; and
passing an electrical current through the conductor strip and the electroplating bath.

3 . The method of claim 1 wherein said providing a plurality of Flat No-Lead Packages comprises providing a molded leadframe assembly having a plurality of integrally connected leadframes and a plurality of dies mounted on corresponding die pad portions of the plurality of integrally connected leadframes the dies being wire bonded to lead portions of the leadframes.

4 . The method of claim 2 wherein said providing a plurality of Flat No-Lead Packages comprises plating exposed lead portions of the plurality of leadframes in the molded leadframe assembly.

5 . The method of claim 4 wherein said providing a plurality of Flat No-Lead Packages comprises singulating the plated molded leadframe assembly into a plurality of Flat No-Lead Packages having plated lead surfaces exposed at a bottom surface thereof and severed and unplated lead surfaces exposed at sidewall portions thereof.

6 . The method of claim 4 further comprising arranging the plurality of Flat No-Lead Packages in a grid.

7 . The method of claim 6 wherein arranging the plurality of Flat No-Lead Packages in a grid comprises placing said plurality of Flat No-Lead Packages in pockets of a tray that are arranged in a grid.

8 . The method of claim 7 wherein said electrically connecting a conductive strip to the plated lead portions of the plurality of Flat No-Lead Packages comprises closing a conductive lid against portions of the Flat No-Lead Packages extending from the pockets.

9 . The method of claim 8 further comprising lifting the conductive lid after the lead surfaces exposed on lateral side surfaces of the Flat No-Lead Packages are plated.

10 . The method of claim 8 further comprising removing the Flat No-Lead Packages from the pockets of the tray.

11 . The method of claim 1 :
wherein said providing comprises providing a plurality of Quad Flat No-Lead Packages having severed, unplated lead surfaces exposed on lateral faces thereof and having plated lead surfaces on bottom faces thereof; and wherein said batch electroplating comprises batch electroplating the severed unplated lead surfaces of said plurality of Quad Flat No-Lead Packages.

12 . A method of making Flat No-Lead Packages comprising:
providing a molded leadframe assembly comprising a plurality of plated leadframes and a plurality of dies mounted on corresponding die pads of the plated leadframes, the dies being wire bonded to leads of the plated leadframes; singulating the plated molded leadframe assembly into a plurality of Flat No-Lead Packages having plated lead surface portions exposed at a bottom faces thereof and unplated severed lead surfaces exposed at lateral faces thereof; electrically connecting a conductive strip to the plated lead portions of the plurality of Flat No-Lead Packages; placing the Flat No-Lead Packages and the connected conductor strip in an electroplating bath; and passing an electrical current through the conductor strip.

13 . The method of claim 12 :
wherein said singulating comprises singulating the plated molded leadframe assembly into a plurality of Quad Flat No-Lead Packages having plated lead surface portions exposed at a bottom surface thereof and unplated severed lead surfaces exposed at sidewall portions thereof; wherein said electrically connecting comprises electrically connecting a conductive strip to the plated lead portions of the plurality of Quad Flat No-Lead Packages; and wherein said placing comprises placing the Quad Flat No-Lead Packages and the connected conductor strip in an electroplating bath.

14 . An assembly for electroplating a plurality of severed lead surfaces that are exposed on sidewall portions of a plurality of Flat No-Lead Packages comprising:
an electroplating bath; and a tray apparatus immersable in said bath comprising a tray bottom plate with a plurality of pockets adapted to support said Flat No-Lead Packages therein and a tray cover plate adapted to make engaging contact with plated leadframe surfaces of Flat No-Lead Packages mounted in said pockets of said tray bottom plate.

15 . The assembly of claim 14 wherein said tray apparatus comprises a tray bottom plate with a plurality of pockets adapted to support said Flat No-Lead Packages therein and a tray cover plate adapted to make engaging contact with plated leadframe surfaces of Flat No-Lead Packages mounted in said pockets of said tray bottom plate.

16 . The assembly of claim 14 wherein said tray bottom plate is an electrically nonconductive plate.

17 . The assembly of claim 14 wherein said tray cover plate is an electrically conductive plate.

18 . The assembly of claim 14 further comprising a current source with an electrode connectable to said tray assembly for producing an electrical current through said Flat No-Lead Packages.

19 . A Flat No-Lead Package comprising:
a block of mold compound having a bottom face and a plurality of lateral side faces; and a plurality of leads exposed on said bottom face; said plurality of leads having severed electroplated end faces exposed on at least one of said plurality of lateral side faces of said block.

20 . The Flat No-Lead package of claim 15 wherein said No-Lead Package is a Quad Flat No-Lead Package.

Assignees

• Texas Instruments Inc

Inventors

• Eugene Lee Lee Han Meng
• Ooi Shu Hui
• Abdul Aziz Anis Fauzi
• Fen Sueann Lim Wei

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/014

  using batch processing · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title