Shift register unit, gate driving circuit and display device

Patent metadata

Field	Value
Publication number	US-2016180964-A1
Application number	US-201314235957-A
Country	US
Kind code	A1
Filing date	Jun 19, 2013
Priority date	Mar 29, 2013
Publication date	Jun 23, 2016
Grant date	—

Abstract

Provided are a shift register unit, a gate driving circuit and a display device, wherein the shift register unit includes: a pull-up module connected to a clock signal line and a signal output terminal; at least two pull-down modules both connected to a low level signal line and the signal output terminal; a control module connected to the pull-up module and the pull-down modules, for controlling the pull-up module to be turned on, so that the pull-up module outputs a high level signal input from the clock signal line to the signal output terminal, and for controlling the at least two pull-down modules to be turned on alternatively, so that the at least two pull-down modules output a low level signal input from the low level signal line to the signal output terminal, and for controlling one of the at least two pull-down modules to be turned on while controlling the other pull-down modules of the at least two pull-down modules to be discharged. The shift register unit can reduce over-bias of a gate of a pull-down TFT effectively, thus improving stability of the shift register unit.

First claim

1 - 13 . (canceled)

14 . A shift register unit, characterized by comprising:
a pull-up module connected to a clock signal line and a signal output terminal; at least two pull-down modules both connected to a low level signal line and the signal output terminal; a control module connected to the pull-up module and the at least two pull-down modules, for controlling the pull-up module to be turned on, so that a high level signal input from the clock signal line is output to the signal output terminal, and for controlling the at least two pull-down modules to be turned on alternatively, so that a low level signal input from the low level signal line is output to the signal output terminal, and for controlling one of the at least two pull-down modules to be turned on while controlling the other pull-down modules of the at least two pull-down modules to be discharged.

15 . The shift register unit of claim 14 , characterized in that the at least two pull-down modules comprise a first TFT and a second TFT, wherein drains of the first TFT and the second TFT are both connected to the signal output terminal, sources thereof are both connected to the low level signal line, a gate of the first TFT is connected to a first signal line, and a gate of the second TFT is connected to a second signal line, and a signal input from the first signal line and a signal input from the second signal line are level signals with inverted amplitudes.

16 . The shift register unit of claim 15 , characterized in that the control module comprises a third TFT and a fourth TFT, wherein a gate of the third TFT is connected to the gate of the first TFT, a drain of the third TFT is connected to the gate of the second TFT, and a source of the third TFT is connected to the low level signal line; a gate of the fourth TFT is connected to the gate of the second TFT, a drain of the fourth TFT is connected to the gate of the first TFT, and a source of the fourth TFT is connected to the low level signal line.

17 . The shift register unit of claim 15 , characterized in that the control module further comprises a scan control sub-module, and the pull-up module comprises a fifth TFT and a capacitor, wherein a gate of the fifth TFT is connected to the scan control sub-module, a drain of the fifth TFT is connected to the clock signal line, and a source of the fifth TFT is connected to the signal output terminal; one terminal of the capacitor is connected to the gate of the fifth TFT, and the other terminal of the capacitor is connected to the drains of the first TFT and the second TFT.

18 . The shift register unit of claim 17 , characterized in that the control module comprises a sixth TFT, wherein a gate of the sixth TFT is connected to the gate of the first TFT, a drain of the sixth TFT is connected to the gate of the fifth TFT, and a source of the sixth TFT is connected to the low level signal line.

19 . The shift register unit of claim 17 , characterized in that the control module further comprises a seventh TFT, wherein a gate of the seventh TFT is connected to the gate of the second TFT, a drain of the seventh TFT is connected to the gate of the fifth TFT, and a source of the seventh TFT is connected to the low level signal line.

20 . A gate driving circuit, characterized by comprising a plurality of shift registers units of claim 14 connected in cascade.

21 . The gate driving circuit of claim 20 , characterized in that the at least two pull-down modules comprise a first TFT and a second TFT, wherein drains of the first TFT and the second TFT are both connected to the signal output terminal, sources thereof are both connected to the low level signal line, a gate of the first TFT is connected to a first signal line, and a gate of the second TFT is connected to a second signal line, and a signal input from the first signal line and a signal input from the second signal line are level signals with inverted amplitudes.

22 . The gate driving circuit of claim 21 , characterized in that,
in a case where the shift register unit is an odd-numbered stage of shift register unit, the gate of the first TFT therein is connected to the gate of the second TFT in a next stage of shift register unit, the gate of the second TFT therein is connected to the gate of the first TFT in the next stage of shift register unit; in a case where the shift register unit is an even-numbered stage of shift register unit, the gate of the first TFT therein is connected to the gate of the second TFT in a previous stage of shift register unit, the gate of the second TFT therein is connected to the gate of the first TFT in the previous stage of shift register unit; the gate of the first TFT in the odd-numbered stage of shift register unit is connected to the first signal line, and the gate of the first TFT in the even-numbered stage of shift register unit is connected to the second signal line.

23 . The gate driving circuit of claim 21 , characterized in that the control module comprises a third TFT and a fourth TFT, wherein a gate of the third TFT is connected to the gate of the first TFT, a drain of the third TFT is connected to the gate of the second TFT, and a source of the third TFT is connected to the low level signal line; a gate of the fourth TFT is connected to the gate of the second TFT, a drain of the fourth TFT is connected to the gate of the first TFT, and a source of the fourth TFT is connected to the low level signal line; and
the control module further comprises a scan control sub-module, and the pull-up module comprises a fifth TFT and a capacitor, wherein a gate of the fifth TFT is connected to the scan control sub-module, a drain of the fifth TFT is connected to the clock signal line, and a source of the fifth TFT is connected to the signal output terminal; one terminal of the capacitor is connected to the gate of the fifth TFT, and the other terminal of the capacitor is connected to the drains of the first TFT and the second TFT.

24 . The gate driving circuit of claim 21 , characterized in that the control module further comprises a tenth TFT, an eleventh TFT and a twelfth TFT;
in a case where the shift register unit is an odd-numbered stage of shift register unit, a gate and a drain of the tenth TFT are both connected to the first signal line, a source of the tenth TFT is connected to a drain of the twelfth TFT; a gate of the twelfth TFT is connected to a signal output terminal of a previous odd-numbered stage of shift register unit, and a source of the twelfth TFT is connected to the low level signal line; a gate of the eleventh TFT is connected to the drain of the twelfth TFT, a drain of the eleventh TFT is connected to the first signal line, and a source of the eleventh TFT is connected to the gate of the first TFT; in a case where the shift register unit is an even-numbered stage of shift register unit, a gate and a drain of the tenth TFT are both connected to the second signal line, a source of the tenth TFT is connected to a drain of the twelfth TFT; a gate of the twelfth TFT is connected to a signal output terminal of a previous even-numbered stage of shift register unit, and a source of the twelfth TFT is connected to the low level signal line; a gate of the eleventh TFT is connected to the drain of the twelfth TFT, a drain of the eleventh TFT is connected to the second signal line, and a source of the eleventh TFT is connected to the gate of the second TFT.

25 . The gate driving circuit of claim 23 , characterized in that the scan control sub-module comprises an eighth TFT and a ninth TFT;
in the case where the shift register unit is an odd-numbered stage of shift register unit, a gate of the eighth TFT is con

Assignees

• Hefei Boe Optoelectronics Tech
• Boe Technology Group Co Ltd

Inventors

• Hu Zuquan
• Wang Guolei
• Ma Rui
• Hu Ming

Classifications

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title