Predicting memory data loss based on temperature accelerated stress time

Patent metadata

Field	Value
Publication number	US-2016180953-A1
Application number	US-201514977191-A
Country	US
Kind code	A1
Filing date	Dec 21, 2015
Priority date	Dec 22, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements may be used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements may lead to improved memory management and data management. That action may include calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.

First claim

We claim:

1 . A method for predicting data loss comprising:
determining, periodically, a data retention for each memory block in a memory device; calculating a rate of change of the data retention based on the periodic calculations; and predicting, with the calculated rate of change, when the data loss in the memory device will occur.

2 . The method of claim 1 wherein the data loss in the memory device is based on a zero-time retention capability of all the memory blocks.

3 . The method of claim 1 wherein the predicting the data loss further comprises:
predicting a life remaining for the memory device based on the data loss.

4 . The method of claim 3 wherein the data loss is predicted when the rate of change of the data retention exceeds a minimum threshold value of an acceptable rate of change of the data retention.

5 . The method of claim 1 further comprising:
identifying, based on the predicting, which of the memory blocks should be refreshed.

6 . The method of claim 5 wherein the memory blocks that should be refreshed are those memory blocks with a predicted upcoming data loss.

7 . The method of claim 1 further comprising:
identifying, based on the predicting, which of the memory blocks should be used for long term storage.

8 . The method of claim 7 wherein the memory blocks that should be used for long term storage are those memory blocks with a low rate of change of the data retention.

9 . The method of claim 1 wherein the determining the data retention comprises:
measuring a voltage distribution of the memory blocks;
calculating a location of the voltage distribution over time; and
quantizing the data retention based on a change in the calculated location.

10 . The method of claim 9 wherein the location comprises a calculation of at least one of a mean, a mode, or a median of the voltage distribution.

11 . The method of claim 1 wherein the determining the data retention is based on an analysis of bit error rate.

12 . A method for analyzing data retention comprising:
performing, with a controller, the following on memory blocks:
calculating, periodically, a data retention for each of the memory blocks;
identifying blocks from the memory blocks with a lowest value of the data retention; and
refreshing the identified blocks.

13 . The method of claim 12 further comprising:
calculating a rate of data retention loss for the identified blocks; and
determining the system data loss based on the rate of data retention lost for the identified blocks.

14 . The method of claim 12 wherein the refreshing comprises moving data from the identified blocks to the memory blocks with a higher value of the data retention.

15 . The method of claim 12 wherein the calculating the data retention for each of the memory blocks comprises:
periodically determining a cell voltage distribution of cells in the memory blocks;
measuring changes in the cell voltage distribution from the periodic determinations; and
calculating changes in a location of the shape of the cell voltage distribution that is indicative of a change in the data retention.

16 . A method for measuring retention loss in a memory device comprising:
calculating, periodically, a data retention for each of block in the memory device; computing, using the periodic calculations of the data retention, a trend for the data retention; measuring, after a power-on of the memory device, the data retention for each of the blocks; and calculating a temperature accelerated stress time based on a comparison of the trend with the measurement of the data retention after the power-on.

17 . The method of claim 16 further comprising:
computing an age of the memory device based on the temperature accelerated stress time.

18 . The method of claim 16 further comprising:
computing a retention lifetime of the memory device based on the temperature accelerated stress time.

19 . The method of claim 16 wherein the temperature accelerated stress time comprises a measurement of data retention loss based on a combination of time and temperature exposure.

20 . A memory system comprising:
a measurement module configured to measure cell voltage values of a population of cells in the memory system; a generation module configured to periodically generate a cell voltage distribution of the population of cells; a comparison module configured to compare the generated cell voltage distribution with a reference cell voltage distribution; and an analysis module configured to calculate a data retention rate for each of the population of cells based on the comparison of the periodically generated cell voltage distribution, the analysis module further configured to predict a temperature accelerated stress time based on the data retention rate.

21 . The memory system of claim 20 wherein the temperature accelerated stress time prediction utilizes the data retention rate and a calculation of a data loss during a power off state to predict a time of the power off state.

Assignees

• Sandisk Technologies Inc

Inventors

• Darragh Neil Richard
• Gorobets Sergey Anatolievich
• Parker Liam Michael

Classifications

• G06F11/008

  Reliability or availability analysis · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G11C16/12

  Programming voltage switching circuits · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title