Non-volatile memory sense circuit

Patent metadata

Field	Value
Publication number	US-2016180944-A1
Application number	US-201414576325-A
Country	US
Kind code	A1
Filing date	Dec 19, 2014
Priority date	Dec 18, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

Voltage is increased on a wordline signal. The wordline signal is applied to a programmed FET and an unprogrammed FET of a memory cell. The programmed FET has a higher threshold voltage than the unprogrammed FET. The programmed FET is connected to a first bitline and the unprogrammed FET is connected to a second bitline. It is determined that the second bitline has reached a threshold voltage. In response to determining the second bitline has reached the threshold voltage, the first bitline is pulled towards ground. A signal is output based on a low voltage of the first bitline and a high voltage of the second bitline.

First claim

What is claimed is:

1 . A method comprising:
increasing a first voltage of a first wordline signal, the first wordline signal applied to a first programmed FET and a first unprogrammed FET of a first memory cell, the first programmed FET having a higher threshold voltage than the first unprogrammed FET, the first programmed FET connected to a first bitline and the first unprogrammed FET connected to a second bitline; and determining the second bitline has reached a first threshold voltage; in response to the determining the second bitline has reached the first threshold voltage, pulling the first bitline towards ground; and outputting a first signal based on a low voltage of the first bitline and a high voltage of the second bitline.

2 . The method of claim 1 , further comprising:
determining the second bitline has reached a second threshold voltage; and in response to the determining the second bitline has reached the second threshold voltage, pulling the second bitline toward a supply voltage.

3 . The method of claim 1 , wherein the first voltage increases from 10% Vdd to 90% Vdd in about 200-800 ps.

4 . The method of claim 1 , further comprising:
precharging the first bitline and the second bitline to ground prior to the increasing the first voltage of the first wordline signal.

5 . The method of claim 1 , further comprising:
precharging the first bitline and the second bitline to ground after the outputting the first signal; increasing a second voltage of a second wordline signal, the second wordline signal applied to a second programmed FET and a second unprogrammed FET of a second memory cell, the second programmed FET having a higher threshold voltage than the second unprogrammed FET, the second programmed FET connected to a second bitline and the second unprogrammed FET connected to a first bitline; and determining the first bitline has reached a second threshold voltage; in response to the determining the first bitline has reached the second threshold voltage, pulling the second bitline towards ground; and outputting a second signal based on a high voltage of the first bitline and a low voltage of the second bitline.

6 . The method of claim 1 , wherein the determining the second bitline has reached the first threshold voltage and the pulling the first bitline towards ground is performed by an NFET, the second bitline applied to a gate on the NFET.

Assignees

• IBM

Inventors

• Kilker Robert E
• Paone Phil C
• Paulsen David P
• Sheets Ii John E
• Uhlmann Gregory J

Classifications

• G11C16/24 Primary

  Bit-line control circuits · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/28

  using differential sensing or reference cells, e.g. dummy cells · CPC title