Apparatus and method for implementing power saving techniques when processing floating point values

Patent metadata

Field	Value
Publication number	US-2016180489-A1
Application number	US-201414581600-A
Country	US
Kind code	A1
Filing date	Dec 23, 2014
Priority date	Dec 23, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

An apparatus and method are described for reducing power when reading and writing graphics data. For example, one embodiment of an apparatus comprises: a graphics processor unit (GPU) to process graphics data including floating point data; a set of registers, at least one of the registers of the set partitioned to store the floating point data; and encode/decode logic to reduce a number of binary 1 values being read from the at least one register by causing a specified set of bit positions within the floating point data to be read out as 0s rather than 1s.

First claim

What is claimed is:

1 . An apparatus comprising:
a graphics processor unit (GPU) to process graphics data including floating point data; a set of registers, at least one of the registers of the set partitioned to store the floating point data; and encode/decode logic to reduce a number of binary 1 values being read from the at least one register by causing a specified set of bit positions within the floating point data to be read out as 0s rather than 1s.

2 . The apparatus as in claim 1 wherein the encode/decode logic comprises a set of exclusive OR (XOR) gates to cause the specified set of bit positions within the floating point data to be read out as 0s rather than 1s.

3 . The apparatus as in claim 2 wherein the XOR gates are applied by XORing a first bit within the specified set of bit positions for a first floating point value with each additional bit within the specified set of bit positions of the first floating point value.

4 . The apparatus as in claim 3 wherein each floating point value comprises a 32-bit single precision floating point value, wherein the specified set of bit positions comprises bits 25 to 29 , wherein the first bit comprises bit 29 and wherein each additional bit XORed with bit 29 comprises bits 25 to 28 .

5 . The apparatus as in claim 2 wherein the XOR gates are applied by XORing a first bit within the specified set of bit positions for a first floating point value with each additional bit within the specified set of bit positions of the first floating point value and wherein the first bit within the specified set of bit positions of the first floating point value is also XORed with each bit within the specified set of bit positions with a plurality of other floating point values.

6 . The apparatus as in claim 5 wherein each floating point value comprises a 32-bit single precision floating point value, wherein the specified set of bit positions comprises bits 25 to 29 , wherein the first bit comprises bit 29 and wherein each additional bit XORed with bit 29 of the first floating point value comprises bits 25 to 28 and wherein the bits of the other floating point values XORed with bit 29 of the first floating point value comprise bits 25 to 29 .

7 . The apparatus as in claim 1 wherein the encode/decode logic comprises a set of inverters to cause the specified set of bit positions within the floating point data to be read out as 0s rather than 1s.

8 . The apparatus as in claim 1 wherein the specified set of bit positions are selected based on a type of graphics data being processed.

9 . The apparatus as in claim 8 wherein the specified set of bit positions are selected based on a determined correlation between the bits within the set of bit positions.

10 . The apparatus as in claim 9 wherein the graphics data comprises Red Green Blue Alpha (RGBA) data.

11 . The apparatus as in claim 10 wherein floating point values of the RGBA data comprise normalized 32-bit single-precision floating point values ranging from 0 to 1.

12 . The apparatus as in claim 11 wherein the specified set of bit positions known to have a high correlation comprises a specified portion of an exponent of the 32-bit single precision floating point value.

13 . The apparatus as in claim 12 wherein the specified set of bit positions comprises bits 25 to 29 .

14 . A method comprising:
determining a specified set of bit positions of floating point graphics data known to have a high correlation; storing the floating point graphics data within at least one register of a set of registers; and reducing a number of binary 1 values being read from the at least one register by causing the specified set of bit positions within the floating point data to be read out from the at least one register as 0s rather than 1s.

15 . The method as in claim 14 wherein causing the specified set of bit positions within the floating point data to be read out from the at least one register as 0s rather than is comprises XORing bits within the specified set of bit positions.

16 . The method as in claim 15 further comprising XORing a first bit within the specified set of bit positions for a first floating point value with each additional bit within the specified set of bit positions of the first floating point value.

17 . The method as in claim 16 wherein each floating point value comprises a 32-bit single precision floating point value, wherein the specified set of bit positions comprises bits 25 to 29 , wherein the first bit comprises bit 29 and wherein each additional bit XORed with bit 29 comprises bits 25 to 28 .

18 . The method as in claim 15 further comprising XORing a first bit within the specified set of bit positions for a first floating point value with each additional bit within the specified set of bit positions of the first floating point value and wherein the first bit within the specified set of bit positions of the first floating point value is also XORed with each bit within the specified set of bit positions with a plurality of other floating point values.

19 . The method as in claim 15 wherein each floating point value comprises a 32-bit single precision floating point value, wherein the specified set of bit positions comprises bits 25 to 29 , wherein the first bit comprises bit 29 and wherein each additional bit XORed with bit 29 of the first floating point value comprises bits 25 to 28 and wherein the bits of the other floating point values XORed with bit 29 of the first floating point value comprise bits 25 to 29 .

20 . The method as in claim 14 wherein causing the specified set of bit positions within the floating point data to be read out from the at least one register as 0s rather than 1s comprises performing an inversion operation of invert the specified set of bit positions.

21 . The method as in claim 14 wherein the graphics data comprises Red Green Blue Alpha (RGBA) data.

22 . The apparatus as in claim 21 wherein floating point values of the RGBA data comprise normalized 32-bit single-precision floating point values ranging from 0 to 1.

23 . The apparatus as in claim 22 wherein the specified set of bit positions known to have a high correlation comprises a specified portion of an exponent of the 32-bit single precision floating point value.

24 . The apparatus as in claim 12 wherein the specified set of bit positions comprises bits 25 to 29 .

25 . A system comprising:
a memory to store instructions and graphics data comprising floating point values; a cache having a plurality of cache levels to cache the instructions and graphics data; a network interface communicatively couple the system over a network; an input/output interface to receive input from a user and responsively cause operations including graphics operations to be performed; and a graphics processor unit (GPU) to process the graphics data including the floating point data; a set of registers, at least one of the registers of the set partitioned to store the floating point data; and encode/decode logic to reduce a number of binary 1 values being read from the at least one register by causing a specified set of bit positions within the floating point data to be read out as 0s rather than 1s.

Assignees

• Intel Corp

Inventors

• Kim Young Moon
• Park Sang Phill

Classifications

• H03M13/1108

  Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping · CPC title

• G09G5/363

  Graphics controllers · CPC title

• H03M7/24

  Conversion to or from floating-point codes · CPC title

• G06F9/3016

  Decoding the operand specifier, e.g. specifier format · CPC title

• G06F1/32

  Means for saving power · CPC title