Load balancing at a graphics processing unit

Patent metadata

Field	Value
Publication number	US-2016180487-A1
Application number	US-201414576828-A
Country	US
Kind code	A1
Filing date	Dec 19, 2014
Priority date	Dec 19, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

A GPU of a processor performers load balancing by enabling and disabling CUs based on the GPU's processing load. A power control module identifies a current processing load of the GPU based on, for example, an activity level of one or more modules of the GPU. The power control module also identifies an expected future processing load of the GPU based on, for example, a number of threads (wavefronts) scheduled to be executed at the GPU. Based on a combination of the current processing load and the expected future processing load, the power control module sets the number of CUs of the GPU that are enabled and the number that are disabled (e.g. clock gated or power gated). By changing the number of enabled CUs based on processing load, the power control module maintains performance at the GPU while conserving power.

First claim

What is clamed is:

1 . A method comprising:
identifying, a first processing load at a graphics processing unit (GPU); and disabling a first set of compute units (CUs) at the GPU based on the first processing load.

2 . The method of claim 1 , wherein identifying the first processing load comprises identifying the processing load based on a current processing load of the GPU and based on an expected future processing load of the GPU.

3 . The method of claim 2 , further comprising identifying the current processing load based on a number of stalled cycles of a first processing unit of the GPU.

4 . The method of claim 3 , wherein the first processing unit comprises an arithmetic logic unit (ALU) of the GPU.

5 . The method of claim 3 , wherein the first processing unit comprises a texture mapping unit of the GPU.

6 . The method of claim 3 , further comprising identifying the current processing load further based on a number of stalled cycles of a second processing unit of the GPU.

7 . The method of claim 2 , further comprising identifying the expected future processing. load of the GPU based on a number of threads scheduled to be executed at the GPU.

8 . The method of claim 1 , wherein identifying the first processing load comprises
identifying the first processing load at a first time, and further comprising: identifying a second processing load at the GPU at a second time and enabling a second set of CUs of the GPU based on the second processing load.

9 . A method, comprising:
identifying a change in a processing load at a graphics processing unit (GPU) based on a current processing load of the GPU and an expected future processing load at the GPU; and in response to identifying the change in the processing load at the GPU, changing a number of activated compute units (CUs) at the GPU.

10 . The method of claim 9 , further comprising:
identifying the current processing load of the GPU based on a ratio of stalled cycles of a processing unit of the GPU to a number of CUs at the GPU.

11 . The method of claim 10 , wherein the processing unit comprises an arithmetic logic unit (ALU) of the GPU.

12 . The method of claim 10 , wherein the processing unit comprises a texture mapping unit of the GPU.

13 . The method of claim 10 further comprising identifying the expected future processing load at the GPU based on a number of threads scheduled for execution at the GPU.

14 . A device, comprising:
a graphics processing unit (GPU) comprising:
a plurality of compute units (CUs);
a performance monitor to identify a change in processing load at the GPU based on a current processing load at the GPU and an expected future processing load at the GPU; and
a power control module to change a power mode of a CU of the plurality of CUs in response to the change in processing load at the GPU.

15 . The device of claim 14 , wherein the performance monitor identifies the processing load based on a current processing load of the GPU and based on an expected future processing load of the GPU.

16 . The device of claim 15 , wherein the performance monitor identifies the current processing load based on a number of stalled cycles of a first processing unit of the GPU.

17 . The device of claim 16 , wherein the first processing unit comprises an arithmetic logic unit (ALU) of the GPU.

18 . The device of claim 16 , wherein the first processing unit comprises a texture mapping unit of the GPU.

19 . The device of claim 16 , further comprising identifying the current processing load further based on a number of stalled cycles of a second processing unit of the GPU.

20 . The device of claim 15 , further comprising identifying the expected future processing load of the GPU based on a number of threads scheduled to be executed at the GPU.

Assignees

• Advanced Micro Devices Inc

Inventors

• Trawczynski Dawid
• Correll Ken
• Presant Stephen D
• Shah Tushar
• Chandrasekaran Ganesh
• Oreifej Rashad

Classifications

• G06T15/04

  Texture mapping · CPC title

• G06T2200/28

  involving image processing hardware · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F9/44

  Arrangements for executing specific programs · CPC title

• G06F9/5083

  Techniques for rebalancing the load in a distributed system · CPC title