Two-part electrical connector

Patent metadata

Field	Value
Publication number	US-2016179733-A1
Application number	US-201414580950-A
Country	US
Kind code	A1
Filing date	Dec 23, 2014
Priority date	Dec 23, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

A two-part electrical connector includes a bottom connector and a top connector. The bottom connector includes a set of electrical contacts, at least one of which has a relatively short effective electrical stub length. The bottom connector may be mounted on a memory bus that also includes a standard memory receiver. In such a system, when driving by a memory bus, the bottom connector generates signal reflections that are significantly reduced compared to conventional systems.

First claim

What is claimed is:

1 . A two-part electrical connector, comprising:
a bottom connector including:
a set of bus connectors structured to be electrically coupled to a memory bus,
at least one mating structure, and
a first set of electrical connectors; and
a top connector including:
a mating structure configured to mechanically interface with the at least one mating structure of the bottom connector,
a second set of electrical connectors, and
a receiving slot structured to receive a memory module.

2 . The two-part electrical connector according to claim 1 in which, when the mating structure of the top connector is mechanically interfaced with the at least one mating structure of the bottom connector, an electrical connection exists between the receiving slot and one or more of the set of bus connectors.

3 . The two-part electrical connector according to claim 1 in which at least one of the electrical connectors in the first set of electrical connectors has an electrical stub length of less than approximately 3 mm.

4 . The two-part electrical connector according to claim 3 in which at least one of the electrical contacts in the first set of electrical connectors has an electrical stub length between approximately 2.25 mm and 2.75 mm.

5 . The two-part electrical connector according to claim 1 in which the receiving slot in the top connector is structured to receive a Double Data Rate Double In-Line Memory Module (DDR DIMM).

6 . A main board including a memory system, the main board comprising:
a Central Processing Unit (CPU) mount; a memory bus electrically coupled to the CPU mount; and a bottom connector of a two-part memory connector, the bottom connector including bus connectors structured to be electrically coupled to the memory bus, and including a first set of electrical contacts, and the bottom connector structured to receive a top connector that can accept a memory module within the top connector.

7 . The main board including a memory system of claim 6 in which the bottom connector comprises a mechanical interface structured to couple to a mechanical interface of the top connector.

8 . The main board including a memory system of claim 7 in which, when the top connector is coupled to the bottom connector, an electrical path is formed between the slot of the top connector and the bus connectors of the bottom connector.

9 . The main board including a memory system of claim 6 in which the bottom connector comprises a set of electrical contacts and in which at least one of the electrical contacts in the set of electrical contacts has an effective electrical stub length of less than approximately 3 mm.

10 . The main board including a memory system of claim 9 in which the at least one of the electrical contacts has an effective electrical stub length between approximately 2.25 mm and 2.75 mm.

11 . A method of making a main board including a memory system, the method comprising:
forming a memory bus on the main board; attaching a first memory connector that is structured to receive a memory module to the memory bus of the main board; and attaching a bottom part of a two-part memory connector to the memory bus of the main board.

12 . The method of making a main board including a memory system according to claim 11 , in which attaching a bottom part of a two-part memory connector to the memory bus of the main board comprises attaching a bottom part of a two-part memory connector that includes a set of contacts at least one of which has an effective electrical stub length of less than approximately 3 mm.

13 . The method of making a main board including a memory system according to claim 11 , in which attaching a bottom part of a two-part memory connector to the memory bus of the main board comprises attaching a bottom part of a two-part memory connector that includes a set of contacts at least one of which has an effective electrical stub length of between approximately 2.25 mm and 2.75 mm.

14 . The method of making a main board including a memory system according to claim 11 , further comprising attaching a top part of the two-part memory connector to the bottom part.

15 . The method of making a main board including a memory system according to claim 14 , further comprising inserting a second memory module into the top part.

16 . A method of sending data signals on a data bus, comprising:
generating data signals; driving the data bus with the signals to a first memory disposed in a first memory connector on the data bus; and at the same time as driving the data bus with the data signals to the first memory, driving the data bus with the data signals to a bottom connector of a two-part data connector that is mounted to the data bus.

17 . The method of sending data signals on a data bus according to claim 16 , further comprising:
attaching a top connector to the bottom connector; and attaching a second memory to the top connector.

18 . The method of sending data signals on a data bus according to claim 17 , in which attaching a top connector to the bottom connector comprises mechanically and electrically coupling the top connector to the bottom connector.

19 . The method of sending data signals on a data bus according to claim 16 , in which the bottom part of the two-part memory connector includes a set of contacts at least one of which has an effective electrical stub length of less than approximately 3 mm.

20 . The method of sending data signals on a data bus according to claim 19 , in which the bottom part of the two-part memory connector includes a set of contacts at least one of which has an effective electrical stub length between approximately 2.25 mm and 2.75 mm.

Assignees

• Intel Corp

Inventors

• Huang Shaowu
• Lee Beom-Taek

Classifications

• G06F13/4072 Primary

  Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002) · CPC title

• H05K2201/10159

  Memory · CPC title

• H01R12/716

  Coupling device provided on the PCB · CPC title

• H01R12/721

  cooperating directly with the edge of the rigid printed circuits · CPC title

• H05K3/366

  substantially perpendicularly to each other (H05K3/361 takes precedence) · CPC title