Push instruction for pushing a message payload from a sending thread to a receiving thread

Patent metadata

Field	Value
Publication number	US-2016179591-A1
Application number	US-201414581144-A
Country	US
Kind code	A1
Filing date	Dec 23, 2014
Priority date	Dec 23, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

A processor core of a data processing system receives a push instruction of a sending thread that requests that a message payload identified by at least one operand of the push instruction be pushed to a mailbox of a receiving thread. In response to receiving the push instruction, the processor core executes the push instruction of the sending thread. In response to executing the push instruction, the processor core initiates transmission of the message payload to the mailbox of the receiving thread. In one embodiment, the processor core initiates transmission of the message payload by transmitting a co-processor request to a switch of the data processing system via an interconnect fabric.

First claim

1 - 7 . (canceled)

8 . A processing unit, comprising:
a memory; and a processor core coupled to the memory, wherein the processor core includes at least one execution unit that, responsive to receiving a push instruction of a sending thread that requests that a message payload identified by at least one operand of the push instruction be pushed to a mailbox of a receiving thread, executes the push instruction, and wherein the processor core, responsive to executing the push instruction, initiates transmission of the message payload to the mailbox of the receiving thread.

9 . The processing unit of claim 8 , wherein the processor core initiates transmission of the message payload by transmitting a co-processor request to a switch in the data processing system via an interconnect fabric of the data processing system.

10 . The processing unit of claim 9 , wherein:
the push instruction includes a co-processor type parameter; the data processing system includes multiple switches including the switch; and the processor core transmits the co-processor type parameter in the co-processor request on the interconnect fabric to identify the switch as responsible for servicing the co-processor request.

11 . The processing unit of claim 9 , wherein:
the switch includes a data structure including a plurality of entries; the push instruction includes a logical window parameter; and the processor core transmits the logical window parameter in the co-processor request on the interconnect fabric to identify a particular entry among the plurality of entries in the data structure in the switch that is to be used to transmit the message payload.

12 . The processing unit of claim 9 , wherein:
the push instruction is a first push instruction; the sending thread includes a second push instruction following the first push instruction in program order; and the processor core executes the first push instruction and thereafter executes the second push instruction only in response to receipt of an indication that the switch claimed the co-processor request.

13 . The processing unit of claim 8 , wherein:
the push instruction includes a report enable parameter that is enabled; and the processor core, responsive to the report enable parameter being enabled, requests notification of the receiving thread of injection of the message payload into the mailbox of the receiving thread.

14 . The processing unit of claim 8 , wherein:
the push instruction includes a completion enable parameter that is enabled; and the processor core, responsive to the completion enable parameter being enabled, requests notification of the sending thread of injection of the message payload into the mailbox of the receiving thread.

15 . A data processing system, comprising:
a memory; an interconnect fabric; a processor core coupled to the memory and to the interconnect fabric, wherein the processor core includes at least one execution unit that, responsive to receiving a push instruction of a sending thread that requests that a message payload identified by at least one operand of the push instruction be pushed to a mailbox of a receiving thread, executes the push instruction, and wherein the processor core, responsive to executing the push instruction, initiates transmission of the message payload to the mailbox of the receiving thread by transmitting a co-processor request to a switch in the data processing system via an interconnect fabric of the data processing system; and a switch coupled to the interconnect fabric, wherein the switch, responsive to the co-processor request, injects the message payload into the mailbox of the receiving thread.

16 . The data processing unit of claim 15 , wherein:
the push instruction includes a co-processor type parameter; the data processing system includes multiple switches including the switch; and the processor core transmits the co-processor type parameter in the co-processor request on the interconnect fabric to identify the switch as responsible for servicing the co-processor request.

17 . The data processing unit of claim 15 , wherein:
the switch includes a data structure including a plurality of entries; the push instruction includes a logical window parameter; and the processor core transmits the logical window parameter in the co-processor request on the interconnect fabric to identify a particular entry among the plurality of entries in the data structure in the switch that is to be used to transmit the message payload.

18 . The data processing unit of claim 15 , wherein:
the push instruction is a first push instruction; the sending thread includes a second push instruction following the first push instruction in program order; and the processor core executes the first push instruction and thereafter executes the second push instruction only in response to receipt of an indication that the switch claimed the co-processor request.

19 . The data processing unit of claim 15 , wherein:
the push instruction includes a report enable parameter that is enabled; and the processor core, responsive to the report enable parameter being enabled, requests notification of the receiving thread of injection of the message payload into the mailbox of the receiving thread.

20 . The data processing unit of claim 15 , wherein:
the push instruction includes a completion enable parameter that is enabled; and the processor core, responsive to the completion enable parameter being enabled, requests notification of the sending thread of injection of the message payload into the mailbox of the receiving thread.

Assignees

• IBM

Inventors

• Arimilli Lakshminarayana B
• Drerup Bernard C
• Frey Bradly G
• Guthrie Guy L
• Irish John D
• Starke William J
• Stuecheli Jeffrey A

Classifications

• G06F9/546 Primary

  Message passing systems or structures, e.g. queues · CPC title

• G06F9/3009

  Thread control instructions · CPC title

• G06F15/167

  using a common memory, e.g. mailbox · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title