Code Generating Method, Compiler, Scheduling Method, Scheduling Apparatus and Scheduling System

Patent metadata

Field	Value
Publication number	US-2016179484-A1
Application number	US-201615058610-A
Country	US
Kind code	A1
Filing date	Mar 2, 2016
Priority date	Sep 3, 2013
Publication date	Jun 23, 2016
Grant date	—

Abstract

A code generating method, a compiler, a scheduling method, an apparatus and a scheduling system where the generated code is an executable code and applied to a heterogeneous system, and the heterogeneous system includes an accelerated processor and a central processing unit (CPU) and the code generating method includes acquiring, by a compiler, resource information of the accelerated processor and resource information of the CPU in order to generate an operable platform list, identifying, by the compiler, accelerable code from first user code, embedding, by the compiler, a hook function and an exception handling function before the accelerable code to form second user code, and compiling, by the compiler, the second user code to obtain the executable code and the executable code generated may automatically implement proper scheduling of processors during execution.

First claim

What is claimed is:

1 . A code generating method, applied to a scheduling system, wherein the scheduling system comprises a heterogeneous system, a compiler, and an executable code, wherein the executable code is applied to the heterogeneous system, wherein the heterogeneous system comprises an accelerated processor and a central processing unit (CPU), and wherein the method comprises:
acquiring, by the compiler, resource information of the accelerated processor and resource information of the CPU in order to generate an operable platform list; identifying accelerable code from first user code according to the resource information of the accelerated processor, wherein the operable platform list comprises all accelerated processors and CPUs; embedding, by the compiler, a hook function and an exception handling function before the accelerable code to form second user code; and compiling, by the compiler, the second user code to obtain the executable code, wherein the executable code comprises executable user code obtained by compiling the hook function and the exception handling function, and first accelerable branch code and second accelerable branch code that are obtained by compiling the accelerable code, wherein the first accelerable branch code is executed by an accelerated processor in the operable platform list, wherein the second accelerable branch code is executed by a CPU in the operable platform list, and wherein a purpose of embedding the hook function and the exception handling function is to use condition control code in the exception handling function to select target processors for the first accelerable branch code and the second accelerable branch code when the hook function is being executed in a process of executing the executable code.

2 . The method according to claim 1 , wherein before the compiler generates the operable platform list, the method further comprises calling a running cost evaluation function to perform running cost evaluation for the accelerated processors and the CPUs.

3 . The method according to claim 2 , wherein before compiling, by the compiler, the second user code to obtain the executable code, the method further comprises selecting, by the compiler, from the accelerated processors, a preset quantity of accelerated processors whose running cost is less than a preset value in order to generate a preferential processor list, wherein the preferential processor list comprises the preset quantity of accelerated processors that are in the operable platform list and whose running cost is less than the preset value, and wherein the first accelerable branch code is executed by an accelerated processor in the preferential processor list.

4 . A scheduling method, applied to a scheduling system, wherein the scheduling system comprises a scheduling apparatus and a heterogeneous system, wherein the heterogeneous system comprises an accelerated processor and a central processing unit (CPU), and wherein the method comprises:
loading and executing, by the scheduling apparatus, executable code generated by a compiler, wherein the executable code comprises executable user code obtained by the compiler by compiling a hook function and an exception handling function, and first accelerable branch code and second accelerable branch code that are obtained by the compiler by compiling accelerable code, wherein the first accelerable branch code is executed by the accelerated processor, and wherein the second accelerable branch code is executed by the CPU; generating, by the scheduling apparatus, an exception when the hook function is being executed; calling, by the scheduling apparatus, the exception handling function; calling a process scheduling interface according to condition control code in the exception handling function; obtaining, using an operable platform list of the process scheduling interface, target processors respectively used for executing the first accelerable branch code and the second accelerable branch code, wherein the operable platform list comprises all accelerated processors and CPUs; and calling, by the scheduling apparatus, the target processors in order to use the target processors to execute the first accelerable branch code and the second accelerable branch code.

5 . The method according to claim 4 , wherein obtaining, by the scheduling apparatus using the operable platform list of the process scheduling interface, target processors respectively used for executing the first accelerable branch code and the second accelerable branch code comprises acquiring, by the scheduling apparatus, from the operable platform list of the process scheduling interface, an accelerated processor and a CPU that have a lowest running cost as the target processors.

6 . The method according to claim 5 , wherein the process scheduling interface further comprises a preferential processor list, and wherein the preferential processor list comprises a preset quantity of accelerated processors that are in the operable platform list and whose running cost is less than a preset value; and
the acquiring, by the scheduling apparatus, from the operable platform list of the process scheduling interface, an accelerated processor and a CPU that have a lowest running cost as the target processors comprises: acquiring, by the scheduling apparatus, from the preferential processor list of the process scheduling interface, the accelerated processor that has the lowest running cost as the target processor that executes the first accelerable branch code; and acquiring, from the operable platform list of the process scheduling interface, the CPU that has the lowest running cost as the target processor that executes the second accelerable branch code.

7 . A device, applied to a scheduling system, wherein the scheduling system comprises a heterogeneous system and an executable code, wherein the executable code is applied to the heterogeneous system, wherein the heterogeneous system comprises an accelerated processor and a central processing unit (CPU), and wherein the device comprises:
a memory storing instructions; and a processor coupled to the memory to execute the instructions to execute a method, and wherein the method comprises: acquiring resource information of the accelerated processing unit and resource information of the CPU in order to generate an operable platform list; identifying accelerable code from first user code according to the resource information of the accelerated processor, wherein the operable platform list comprises all accelerated processors and CPUs; embedding a hook function and an exception handling function before the accelerable code to form second user code; and compiling the second user code to obtain the executable code, wherein the executable code comprises executable user code obtained by compiling the hook function and the exception handling function, and first accelerable branch code and second accelerable branch code that are obtained by compiling the accelerable code, wherein the first accelerable branch code is executed by an accelerated processor in the operable platform list, wherein the second accelerable branch code is executed by a CPU in the operable platform list, and wherein a purpose of embedding the hook function and the exception handling function is to use condition control code in the exception handling function to select target processors for the first accelerable branch code and the second accelerable branch code when the hook function is being executed in a process of executing the executable code.

8 . The device according to claim 7 , wherein before the processor generates the operable platform list, the method further comprises calling a running cost evaluation function to perfor

Assignees

• Huawei Tech Co Ltd

Inventors

• Yan Youliang
• Zheng Rongfu

Classifications

• G06F11/3604

  Analysis of software for verifying properties of programs (testing of software G06F11/3668) · CPC title

• G06F9/5027

  the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title

• G06F9/5044

  considering hardware capabilities · CPC title

• G06F9/445

  Program loading or initiating (bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57) · CPC title

• G06F8/40 Primary

  Transformation of program code · CPC title