Hardware-based performance equalization for storage devices

Patent metadata

Field	Value
Publication number	US-2016179373-A1
Application number	US-201414574527-A
Country	US
Kind code	A1
Filing date	Dec 18, 2014
Priority date	Dec 18, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

An apparatus includes a register memory and circuitry. The register memory is configured to hold a minimal value specified for a performance measure of a given type of memory access commands, whose actual performance measures vary among memory devices. The circuitry is configured to receive a memory access command of the given type, to execute the received memory access command in one or more memory devices, and to acknowledge the memory access command not before reaching the minimal value stored in the register memory.

First claim

1 . An apparatus, comprising:
a register memory configured to hold a minimal value specified for a performance measure of a given type of memory access commands, wherein actual performance measures of the given type of memory access commands vary among memory devices; and circuitry configured to: receive a memory access command of the given type; execute the received memory access command in one or more memory devices; and acknowledge the memory access command not before reaching the minimal value stored in the register memory.

2 . The apparatus according to claim 1 , wherein the register memory is configured to hold multiple minimal values specified for respective different types of the memory access commands, and wherein the circuitry is configured to: identify a type of the received memory access command; and acknowledge the received memory access command not before reaching the respective minimal value specified for the identified type.

3 . The apparatus according to claim 1 , wherein the memory access commands comprise write commands, and wherein the performance measure comprises write duration.

4 . The apparatus according to claim 1 , wherein the performance measure comprises a duration of executing the memory access commands of the given type, and wherein the circuitry is configured to: initialize a timer to measure the minimal value stored in the register memory; start the timer upon receiving the memory access command for execution, and acknowledge the memory access command not before the timer expires.

5 . The apparatus according to claim 1 , wherein the register memory or the circuitry is configured to reconfigure the minimal value in response to an external instruction.

6 . The apparatus according to claim 1 , wherein the register memory and the circuitry are integrated in the given memory device.

7 . The apparatus according to claim 1 , wherein the register memory and the circuitry are integrated in a controller that stores data in the given memory device.

8 . A system, comprising:
one or more memory devices; a processor; and a performance equalization unit configured to:
hold a minimal value specified for a performance measure of a given type of memory access commands, wherein actual performance measures of the given type of memory access commands vary among memory devices;
receive from the processor a memory access command of the given type;
execute the received memory access command in the one or more memory devices; and
acknowledge the memory access command not before reaching the minimal value stored in the register memory.

9 . The system according to claim 8 , wherein the performance equalization unit is configured to: hold multiple minimal values specified for respective different types of the memory access commands; identify a type of the received memory access command; and acknowledge the received memory access command not before reaching the respective minimal value specified for the identified type.

10 . The system according to claim 8 , wherein the memory access commands comprise write commands, and wherein the performance measure comprises write duration.

11 . The system according to claim 8 , wherein the performance measure comprises a duration of executing the memory access commands of the given type, and wherein the performance equalization unit is configured to: initialize a timer to measure the minimal value stored in the register memory; start the timer upon receiving the memory access command for execution; and acknowledge the memory access command not before the timer expires.

12 . The system according to claim 8 , wherein the performance equalization unit is configured to reconfigure the minimal value in response to an external instruction.

13 . The system according to claim 8 , wherein the performance equalization unit is integrated in the one or more memory devices.

14 . The system according to claim 8 , wherein the performance equalization unit is integrated in a memory controller that comprises the processor.

15 . A method, comprising:
holding in a register memory a minimal value specified for a performance measure of a given type of memory access commands, whose actual performance measures vary among memory devices; receiving a memory access command of the given type, and executing the received memory access command in one or more memory devices; and acknowledging the memory access command not before reaching the minimal value.

16 . The method according to claim 15 , wherein holding the minimal value comprises holding multiple minimal values specified for respective different types of the memory access commands, and wherein acknowledging the memory access command comprises identifying a type of the received memory access command, and acknowledging the received memory access command not before reaching the respective minimal value specified for the identified type.

17 . The method according to claim 15 , wherein the memory access commands comprise write commands, and wherein the performance measure comprises write duration.

18 . The method according to claim 15 , wherein the performance measure comprises a duration of executing the memory access commands of the given type, and wherein acknowledging the memory access command comprises initializing a timer to measure the minimal value stored in the register memory, starting the timer upon receiving the memory access command for execution, and acknowledging the memory access command not before the timer expires.

19 . The method according to claim 15 , and comprising reconfiguring the minimal value in response to an external instruction.

Assignees

• Apple Inc

Inventors

• Erez Liran
• Ben-Yehuda Guy
• Meir Avraham Poza
• Isachar Ori

Classifications

• G11C7/1045

  Read-write mode select circuits · CPC title

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title

• G11C7/1063

  Control signal output circuits, e.g. status or busy flags, feedback command signals · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title