Thin film display panel and liquid crystal display device including the same

Patent metadata

Field	Value
Publication number	US-2016178945-A1
Application number	US-201514676459-A
Country	US
Kind code	A1
Filing date	Apr 1, 2015
Priority date	Dec 17, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

An exemplary embodiment of the present system and method provides a thin film display panel including: an insulation substrate configured to include a red area, a blue area, a green area, and a white area; a gate line and a data line disposed on the insulation substrate; a step compensating member disposed in the white area on the insulation substrate; a red color filter, a green color filter, and a blue color filter respectively disposed at the red area, the blue area, and the green area on the insulation substrate; a planarization layer configured to cover the red color filter, the green color filter, the blue color filter, and the step compensating member; and a plurality of pixel electrodes formed on the planarization layer.

First claim

What is claimed is:

1 . A thin film display panel comprising:
an insulation substrate configured to include a red area, a blue area, a green area, and a white area; a gate line and a data line disposed on the insulation substrate; a step compensating member disposed in the white area on the insulation substrate; a red color filter, a green color filter, and a blue color filter respectively disposed at the red area, the blue area, and the green area on the insulation substrate; a planarization layer configured to cover the red color filter, the green color filter, the blue color filter, and the step compensating member; and a plurality of pixel electrodes formed on the planarization layer.

2 . The thin film display panel of claim 1 , wherein the step compensating member includes a same material as that of the gate line and the data line.

3 . The thin film display panel of claim 2 , wherein the step compensating member includes a portion of a gate insulating layer covering the gate line and a portion of a passivation layer covering the data line.

4 . The thin film display panel of claim 1 , wherein a height difference between the pixel electrodes of the white pixel area and the other pixel areas is equal to or smaller than 0.2 μm.

5 . The thin film display panel of claim 1 , further comprising
a thin film transistor connected to the gate line and the data line, and including a semiconductor unit and an ohmic contact layer, wherein the step compensating member includes a same material as that of the semiconductor unit and the ohmic contact layer.

6 . The thin film display panel of claim 5 , wherein the step compensating member includes a same material as that of the gate line and the data line.

7 . The thin film display panel of claim 6 , wherein a height difference between the pixel electrodes of the white pixel area and the other pixel areas is equal to or smaller than 0.2 μm.

8 . A manufacturing method of a thin film display panel, the method comprising:
forming a gate line and a first step compensating member on an insulation substrate; forming a gate insulating layer on the gate line; forming a semiconductor unit on the gate insulating layer; forming a data line and a second step compensating member on the semiconductor unit; forming a passivation layer on the data line; forming a color filter on the passivation layer; forming a planarization layer on the color filter; and forming a pixel electrode on the planarization layer, wherein the first step compensating member and the second step compensating member overlap with each other without overlapping with the color filter.

9 . The manufacturing method of claim 8 , wherein the gate insulating layer is formed to cover the first step compensating member, and the passivation layer is formed to cover the second step compensating member.

10 . The manufacturing method of claim 8 , wherein forming the semiconductor unit includes forming a third step compensating member that overlaps the first step compensating member.

11 . A liquid crystal display comprising:
a thin film display panel configured to include an insulation substrate including a red area, a blue area, a green area, and a white area, a gate line and a data line disposed on the insulation substrate, a step compensating member disposed in the white area on the insulation substrate, a red color filter, a green color filter, and a blue color filter respectively disposed at the red area, the blue area, and the green area on the insulation substrate, a planarization layer covering the red color filter, the green color filter, the blue color filter, and the step compensating member, and a plurality of pixel electrodes formed on the planarization layer; a second insulation substrate configured to face the first insulation substrate; an opposing display panel configured to include a common electrode formed on the second insulation substrate; and a liquid crystal layer configured to be filled in a space between the thin film display panel and the opposing display panel.

12 . The liquid crystal display of claim 11 , wherein the step compensating member includes a same material as that of the gate line and the data line.

13 . The liquid crystal display of claim 12 , wherein the step compensating member includes a portion of a gate insulating layer covering the gate line and a portion of a passivation layer covering the data line.

14 . The liquid crystal display of claim 13 , wherein the thin film display panel further includes a thin film transistor connected to the gate line and the data line, and including a semiconductor unit and an ohmic contact layer, and
the step compensating member includes a same material as that of the semiconductor unit and the ohmic contact layer.

Assignees

• Samsung Display Co Ltd

Inventors

• Ryu Soo Hye
• Lee Yun Ho
• Lee Yui Ku
• Huh Chul

Classifications

• G02F1/1368 Primary

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/133514

  Colour filters · CPC title

• Y10S359/90

  Methods · CPC title

• G02F1/133

  Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements (arrangements or circuits for control of liquid crystal elements in a matrix, not structurally associated with these elements G09G3/36) · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title