Substrate structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2016174390-A1
Application number	US-201615052885-A
Country	US
Kind code	A1
Filing date	Feb 25, 2016
Priority date	Apr 28, 2014
Publication date	Jun 16, 2016
Grant date	—

Abstract

A substrate structure includes a dielectric layer, a metal foil, a patterned metal layer, a first patterned solder-resist layer and a second patterned solder-resist layer. The dielectric layer includes a first surface and a second surface, and the first surface has a plurality of recesses. The metal foil is disposed on the second surface. The patterned metal layer is disposed on the first surface, the patterned metal layer has a plurality of openings, and the openings are respectively corresponding to and expose the recesses. The first patterned solder-resist layer is filled in each of the recesses and corresponding to each of the openings. A top surface of the first patterned solder-resist layer is substantially coplanar with a top surface of the patterned metal layer. The second patterned solder-resist layer is disposed on the first patterned solder-resist layer and in the openings, and covers a portion of the patterned metal layer.

First claim

What is claimed is:

1 . A substrate structure, comprising:
a dielectric layer comprising a first surface and a second surface opposite to the first surface, the first surface having a plurality of recesses; a metal foil disposed on the second surface; a patterned metal layer disposed on the first surface, the patterned metal layer having a plurality of openings, the openings respectively corresponding to and exposing the recesses; a first patterned solder-resist layer filled in each of the recesses and corresponding to each of the openings, a top surface of the first patterned solder-resist layer being substantially coplanar with a top surface of the patterned metal layer; and a second patterned solder-resist layer disposed on the first patterned solder-resist layer and in the openings of the patterned metal layer, and covering a portion of the patterned metal layer.

2 . The substrate structure as claimed in claim 1 , further comprising:
a surface finish layer covering the exposed portion of the patterned metal layer.

3 . The substrate structure as claimed in claim 1 , further comprising:
a surface finish layer covering the patterned metal layer and the metal foil.

4 . The substrate structure as claimed in claim 3 , wherein each of the surface finish layers comprises an OSP layer, a Ni/Au layer, a silver layer, a tin layer, a bismuth layer, a Pd/Ni layer, a Pd/Cu layer or a Sn—Bi alloy layer.

5 . A manufacturing method of a substrate structure, comprising:
providing a substrate, the substrate comprising a supporting layer, two release layers and two base metal layers, the two release layers being disposed on two opposite surfaces of the supporting layer respectively, the two base metal layers covering the two release layers respectively; forming two first patterned solder-resist layers on each of the base metal layers; laminating two stacking layers on each of the base metal layers, each of the stacking layers covering the corresponding first patterned solder-resist layer, wherein each of the stacking layers comprises a dielectric layer and a metal foil, and each of the dielectric layers is disposed between the corresponding base metal layer and the corresponding metal foil; separating each of the base metal layers from the release layer to remove the supporting layer; patterning each of the base metal layers to form a patterned metal layer on each of the stacking layers, each of the patterned metal layers at least partially exposing each of the first patterned solder-resist layers; and forming two second patterned solder-resist layers on each of the exposed first patterned solder-resist layers, each of the second patterned solder-resist layers partially covering the corresponding the patterned metal layers.

6 . The manufacturing method of a substrate structure as claimed in claim 5 , wherein the step of patterning each of the base metal layers comprises etching.

7 . The manufacturing method of a substrate structure as claimed in claim 5 , further comprising:
forming a surface finish layer on each of the patterned metal layers to cover the exposed portion of the patterned metal layer.

8 . The manufacturing method of a substrate structure as claimed in claim 5 , further comprising:
forming a surface finish layer on each of the patterned metal layers and each of the metal foils.

9 . The manufacturing method of a substrate structure as claimed in claim 5 , wherein each of the release layers comprises a fluorine release film, a PE release film, or a PET release film.

10 . A substrate structure, comprising:
a dielectric layer comprising a first surface and a second surface opposite to the first surface, the first surface having a plurality of recesses; a metal foil disposed on the second surface; a first patterned solder-resist layer filled into each of the recesses, a top surface of the first patterned solder-resist layer being coplanar with the first surface; a patterned metal layer disposed on the first surface and having a plurality of openings at least partially exposing the first patterned solder-resist layer; and a second patterned solder-resist layer disposed on the first patterned solder-resist layer and in the openings of the patterned metal layer, and covering a portion of the patterned metal layer.

11 . The substrate structure as claimed in claim 10 , further comprising:
a surface finish layer covering the exposed portion of the patterned metal layer.

12 . The substrate structure as claimed in claim 10 , further comprising:
a surface finish layer covering the patterned metal layer and the metal foil.

Assignees

• Subtron Technology Co Ltd

Inventors

• Wang chao-min

Classifications

• H10P72/7424

  used as a support during the manufacture of self-supporting substrates · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W70/68

  Shapes or dispositions thereof · CPC title

• H10W70/66

  Conductive materials thereof · CPC title