Enhanced Data Bus Invert Encoding for OR Chained Buses

Patent metadata

Field	Value
Publication number	US-2016173134-A1
Application number	US-201414569985-A
Country	US
Kind code	A1
Filing date	Dec 15, 2014
Priority date	Dec 15, 2014
Publication date	Jun 16, 2016
Grant date	—

Abstract

Methods and apparatus relating to enhanced Data Bus Invert (EDBI) encoding for OR chained buses are described. In an embodiment, incoming data on a bus is encoded based at least in part on a determination of whether a next data value on the bus is going to transitioning from a valid value to a parked state. Other embodiments are also disclosed.

First claim

1 . An apparatus comprising:
a receiver to be coupled to a data bus, the receiver to receive incoming data; control logic, coupled to the receiver, to determine whether a next data value on the data bus is going to transition from a valid value to a parked state; and encode logic to encode the incoming data based at least in part on the determination of whether the next data value on the bus is going to transitioning from the valid value to the parked state.

2 . The apparatus of claim 1 , wherein the encode logic is to encode the incoming data based at least in part on comparison of: a hamming distance between a present bus value and the next data value, and a weight of the next data value.

3 . The apparatus of claim 1 , wherein the encode logic is to cause an inversion of the next data value at least in part based on comparison of a weight of the next data value and a width of the bus.

4 . The apparatus of claim 1 , wherein the incoming data is to originate from a plurality of sources.

5 . The apparatus of claim 4 , wherein the plurality of sources are to comprise a plurality of buses.

6 . The apparatus of claim 4 , wherein the plurality of sources are to be coupled in a daisy chain configuration.

7 . The apparatus of claim 4 , wherein the plurality of sources are to be coupled in an OR tree configuration.

8 . The apparatus of claim 1 , wherein the encode logic is to encode the incoming data from the plurality of buses with an extra bit.

9 . The apparatus of claim 1 , wherein the encode logic, the control logic, a processor having one or more processor cores, and memory are on a same integrated device.

10 . A method comprising:
encoding incoming data on a bus based at least in part on a determination of whether a next data value on the bus is going to transitioning from a valid value to a parked state.

11 . The method of claim 10 , further comprising encoding the incoming data based at least in part on comparison of: a hamming distance between a present bus value and the next data value, and a weight of the next data value.

12 . The method of claim 10 , further comprising causing an inversion of the next data value at least in part based on comparison of a weight of the next data value and a width of the bus.

13 . The method of claim 10 , wherein the incoming data originates from a plurality of sources.

14 . The method of claim 13 , wherein the plurality of sources comprise a plurality of buses.

15 . The method of claim 13 , wherein the plurality of sources are coupled in a daisy chain configuration.

16 . The method of claim 13 , wherein the plurality of sources are coupled in an OR tree configuration.

17 . The method of claim 10 , further comprising encoding the incoming data from the plurality of buses with an extra bit.

18 . A system comprising:
a display device; a processor coupled to the display device to cause the display device to display one or more images stored in memory; logic to encode incoming data on a bus, coupled to the processor, based at least in part on a determination of whether a next data value on the bus is going to transitioning from a valid value to a parked state.

19 . The system of claim 18 , wherein the logic is to encode the incoming data based at least in part on comparison of: a hamming distance between a present bus value and the next data value, and a weight of the next data value.

20 . The system of claim 18 , wherein the logic is to cause an inversion of the next data value at least in part based on comparison of a weight of the next data value and a width of the bus.

21 . The system of claim 18 , wherein the incoming data is to originate from a plurality of sources.

22 . The system of claim 21 , wherein the plurality of sources are to comprise a plurality of buses.

23 . The system of claim 21 , wherein the plurality of sources are to be coupled in a daisy chain configuration.

24 . The system of claim 21 , wherein the plurality of sources are to be coupled in an OR tree configuration.

25 . The system of claim 18 , wherein the logic is to encode the incoming data from the plurality of buses with an extra bit.

Assignees

• Intel Corp

Inventors

• Kwon Kon-Woo
• Somasekhar Dinesh
• Park Sang Phill

Classifications

• H03M13/19 Primary

  Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes · CPC title

• G06F13/4265

  on a point to point bus (G06F13/4247, G06F13/4282 take precedence) · CPC title

• G06F13/4221 Primary

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F13/4234

  being a memory bus · CPC title

• G06F13/4252 Primary

  using a handshaking protocol · CPC title