Circuit generating an analog signal using a part of a sigma-delta adc

Patent metadata

Field	Value
Publication number	US-2016173121-A1
Application number	US-201514715022-A
Country	US
Kind code	A1
Filing date	May 18, 2015
Priority date	Dec 16, 2014
Publication date	Jun 16, 2016
Grant date	—

Abstract

The circuit generates an analog output signal which may be used to test a sigma-delta ADC. A digital waveform generator supplies a digital signal to a DAC to convert the digital signal into an analog signal. A filter filters the analog signal to obtain the analog output signal. The DAC is a DAC of a sigma-delta ADC and the filter comprises a filter of the sigma/delta ADC. A multiplexer 34 supplies the digital signal to the DAC in a generator mode wherein the circuit converts the digital signal into the analog output signal using the part of the sigma-delta ADC, or to supply a quantized analog output signal to the DAC in normal mode wherein the sigma-delta ADC converts its analog input signal into the quantized analog output signal.

First claim

1 . A circuit for generating an analog output signal by using a part of a sigma-delta ADC in a generator mode or for operating as a sigma-delta ADC in a normal mode, the circuit comprising a digital waveform generator and a sigma-delta ADC:
the digital waveform generator having a generator output for supplying a digital signal, the sigma-delta ADC comprising: an ADC input for receiving an analog input signal, a switch input for receiving a first switch signal, an analog filter comprising a filter input, and a filter output for supplying an analog filtered signal, a quantizer comprising a quantizer input coupled to the filter output for receiving the analog filtered signal and a quantizer output for converting the analog filtered signal into a digital data stream, a DAC comprising a DAC input and a DAC output, and a subtractor comprising a first subtractor input coupled to the DAC output, a second subtractor input coupled to the ADC input via a first switch and a subtractor output being coupled to the filter input, and the circuit comprising a multiplexer comprising a first multiplexer input coupled to the quantizer output for receiving the digital data stream, a second multiplexer input coupled to the generator output for receiving the digital signal, a multiplexer selection input for receiving the first switch signal and a multiplexer output coupled to the DAC input for supplying either (i) the digital signal to the DAC input when the first switch signal indicates the generator mode wherein the part of the sigma-delta ADC used for generating the analog output signal comprises the analog filter and the analog output signal is output from the circuit, or (ii) for coupling the quantizer output to the DAC input when the first switch signal indicates the normal mode wherein the sigma-delta ADC is arranged for converting the analog input signal into the digital data stream.

2 . A circuit as claimed in claim 1 , wherein the sigma delta ADC comprises a first switch function arranged between the ADC input and the second subtractor input for preventing the analog input signal reaching the second subtractor input when the first switch signal indicates the generator mode.

3 . A circuit as claimed in claim 1 , wherein the sigma-delta ADC comprises a second switch arranged between the filter output and the quantizer input for disconnecting the quantizer input from the filter output when the first switch signal indicates the generator mode.

4 . A circuit as claimed in claim 1 , further comprising a circuit to be tested, the circuit to be tested having a further input for receiving the analog filtered signal as a test signal.

5 . A circuit as claimed in claim 4 , wherein the circuit to be tested is a further sigma-delta ADC comprising an analog portion comprising:
a further ADC input for receiving a further analog input signal, a further subtractor coupled to the further ADC-input and to an output of a further DAC for subtracting an analog quantized signal supplied by the further DAC from the analog filtered signal to obtain an analog difference signal, a further analog filter coupled to the further subtractor for filtering the analog difference signal into a filtered difference signal, a further quantizer coupled to the further analog filter for receiving the filtered difference signal and coupled to the second DAC for supplying a further digital data stream to the further DAC, and the further DAC being arranged to convert the further digital data stream into the analog quantized signal, wherein the circuit is arranged for receiving the analog filtered signal as the analog difference signal.

6 . A circuit as claimed in claim 5 , wherein the further sigma-delta ADC comprises a third switch being arranged for coupling the further analog input signal to the subtractor in the normal mode wherein the further sigma-delta ADC is arranged for converting the further analog input signal into the further digital quantized stream, or for coupling the analog filtered signal to the subtractor in the generator mode when the analog portion of the further sigma-delta ADC is tested by applying the analog filtered signal.

7 . A circuit as claimed in claim 5 , wherein the first mentioned analog filter has a transfer function H′(s) switchable in response to the first switch signal between an integrating function when the first switch signal indicates that the first mentioned sigma-delta ADC is in normal mode and a low-pass filter function when the first switch signal indicates that the first mentioned sigma-delta ADC is in generator mode.

8 . A circuit as claimed in claim 7 , wherein the first mentioned analog filter comprises filter circuitry equal to the circuitry of the further analog filter, the filter circuitry comprising integrating capacitors to obtain integrating properties and additional provisions for changing the transfer function H′(s) into a low-pass filter in response to the first switch signal indicating that the first mentioned sigma-delta ADC is in generator mode, the additional provisions comprising resistors and associated switches being arranged for coupling the resistors in parallel with the associated integrator capacitors when the first switch signal indicates that the first mentioned sigma-delta ADC is in generator mode.

9 . A circuit as claimed in claim 7 , wherein the first mentioned analog filter is identical to the further analog filter, both having low-pass filter characteristics.

10 . A circuit as claimed in claim 1 , wherein the digital waveform generator further comprises:
a clock generator for supplying a clock signal, and a controller comprising a controller input for receiving an input control signal and being coupled to the clock generator, and wherein the controller is arranged for controlling the clock generator to control a repetition frequency of the clock signal for obtaining the second particular bit rate to correspond to a bit rate of the digital data stream and for controlling the digital generator to obtain the second particular number of bits to correspond to the number of bits of the digital data stream.

11 . A system comprising the circuit as claimed in claim 1 and a further circuit comprising an input for receiving the analog output signal being the analog filtered signal.

12 . A system as claimed in claim 4 , wherein the circuit for generating the analog output signal and the circuit to be tested are integrated on a same chip.

13 . A system as claimed in claim 5 , wherein the circuit for generating the analog output signal and the further sigma-delta ADC are integrated on a same chip.

14 . A system as claimed in claim 1 , wherein the digital waveform generator is arranged for generating the digital test signal to obtain the analog output signal being a test signal for testing a sigma-delta ADC.

15 . A method of generating an analog output signal by using a part of a sigma-delta ADC in a generator mode or for performing a sigma-delta ADC operation in a normal mode, the method comprising:
generating a digital signal, and a sigma-delta Analog to Digital conversion comprising: receiving an analog input signal, receiving a first switch signal, filtering an analog filter input signal with an analog filter to obtain an analog filtered signal, quantizing the analog filtered signal into a digital data stream, digital to analog converting a DAC input signal into a DAC output signal, subtracting the DAC output signal from a further subtractor input signal to supply the analog filter input signal, selecting the further subtractor input signal to be the analog input signal when

Assignees

• Doare Olivier Vincent
• Hales Rex Kenton
• Freescale Semiconductor Inc

Inventors

• Doare Olivier Vincent
• Hales Rex Kenton

Classifications

• H03M3/39 Primary

  Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators (of digital delta-sigma modulators H03M7/3004) · CPC title

• H03M3/378 Primary

  Testing · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title