N-path cascode transistor output switch for a digital to analog converter

Patent metadata

Field	Value
Publication number	US-2016173113-A1
Application number	US-201514958051-A
Country	US
Kind code	A1
Filing date	Dec 3, 2015
Priority date	Dec 12, 2014
Publication date	Jun 16, 2016
Grant date	—

Abstract

Techniques are provided for a switched output digital to analog converter employing an N-path cascode output switch. An example system may include a plurality of cascode transistors coupled in parallel to an output stage of a current mode digital to analog converter (DAC) circuit. The system may also include a plurality of control ports, each of the control ports coupled to a gate of one of the cascode transistors. The system may further include a plurality of output ports, each output port coupled to one of the cascode transistors. The cascode transistors are configured to switch the output stage of the DAC to the output port of the transistor in response to a routing control signal applied to the control port of the transistor. The cascode transistors are High Electron Mobility Transistors (HEMT) fabricated from Gallium Nitride.

First claim

What is claimed is:

1 . A switch comprising:
a plurality of cascode transistors coupled in parallel to an output stage of a current mode digital to analog converter (DAC) circuit; a plurality of control ports, each of the control ports coupled to a gate of one of the cascode transistors; and a plurality of output ports, each output port coupled to one of the cascode transistors, wherein the cascode transistors are configured to switch the output stage of the DAC to the output port of the transistor in response to a routing control signal applied to the control port of the transistor.

2 . The switch of claim 1 , wherein the cascode transistors are High Electron Mobility Transistors (HEMT) fabricated from Gallium Nitride.

3 . The switch of claim 1 , wherein the cascode transistors are High Electron Mobility Transistors (HEMT) fabricated from Gallium Arsenide.

4 . The switch of claim 1 , wherein the cascode transistors are Bipolar Junction Transistors fabricated from Indium Phosphide.

5 . The switch of claim 1 , wherein the cascode transistors are Field Effect Transistors fabricated from Silicon.

6 . The switch of claim 1 , wherein the cascode transistors are Field Effect Transistors fabricated from Gallium Nitride.

7 . The switch of claim 1 , wherein the cascode transistors are Field Effect Transistors fabricated from Gallium Arsenide.

8 . The switch of claim 1 , wherein the DAC circuit comprises Hetero Junction Bipolar Transistors (HBT) fabricated from Indium Phosphide.

9 . The switch of claim 1 , wherein the DAC circuit and the switch are fabricated based on different fabrication technologies and combined within a heterogeneous integrated circuit process.

10 . The switch of claim 1 , wherein each of the cascode transistors are configured as a differential pair of transistors.

11 . The switch of claim 1 , wherein the DAC circuit is configured to generate a signal at the output stage, the signal comprising a peak current in the range of 90 milliamps to 200 milliamps and a frequency greater than 40 Gigahertz.

12 . A communications system comprising:
a current mode digital to analog converter (DAC) circuit to generate an analog signal at an output stage of the DAC for transmission; a switch comprising:
a plurality of cascode transistors coupled in parallel to the output stage of the DAC circuit;
a plurality of control ports, each of the control ports coupled to a gate of one of the cascode transistors;
a plurality of output ports, each output port coupled to one of the cascode transistors, wherein the cascode transistors are configured to switch the output stage of the DAC to the output port of the transistor in response to a routing control signal applied to the control port of the transistor; and
a plurality of transmitter circuits to transmit the analog signal, each of the transmitter circuits coupled to one of the output ports of the switch.

13 . The communications system of claim 12 , wherein the cascode transistors are High Electron Mobility Transistors (HEMT) fabricated from Gallium Nitride or Gallium Arsenide.

14 . The communications system of claim 12 , wherein the cascode transistors are Bipolar Junction Transistors fabricated from Indium Phosphide.

15 . The communications system of claim 12 , wherein the cascode transistors are Field Effect Transistors fabricated from Silicon or Gallium Nitride or Gallium Arsenide.

16 . The communications system of claim 12 , wherein the DAC circuit comprises Hetero Junction Bipolar Transistors (HBT) fabricated from Indium Phosphide.

17 . The communications system of claim 12 , wherein each of the cascode transistors are configured as a differential pair of transistors.

18 . The communications system of claim 12 , wherein the DAC circuit generated analog signal comprises a peak current in the range of 90 milliamps to 200 milliamps and a frequency greater than 40 Gigahertz.

19 . The communications system of claim 12 , further comprising a plurality of bandpass filter circuits, each of the filter circuits coupled between one of the output ports of the switch and the associated transmitter circuit.

20 . A method for fabricating a switched output digital to analog converter, the method comprising:
coupling a plurality of cascode transistors in parallel to an output stage of a current mode digital to analog converter (DAC) circuit; providing a plurality of control ports, each of the control ports coupled to a gate of one of the cascode transistors; and providing a plurality of output ports, each output port coupled to one of the cascode transistors, wherein the cascode transistors are configured to switch the output stage of the DAC to the output port of the transistor in response to a routing control signal applied to the control port of the transistor.

21 . The method of claim 20 , further comprising configuring the cascode transistors as High Electron Mobility Transistors (HEMT) fabricated from Gallium Nitride or Gallium Arsenide.

22 . The method of claim 20 , further comprising configuring the cascode transistors as Bipolar Junction Transistors fabricated from Indium Phosphide.

23 . The method of claim 20 , further comprising configuring the cascode transistors as Field Effect Transistors fabricated from Silicon or Gallium Nitride or Gallium Arsenide.

24 . The method of claim 20 , wherein the DAC circuit comprises Hetero Junction Bipolar Transistors (HBT) fabricated from Indium Phosphide.

25 . The method of claim 20 , further comprising configuring each of the cascode transistors as a differential pair of transistors.

26 . The method of claim 20 , further comprising fabricating the DAC circuit and the switch based on different fabrication technologies and combining the DAC circuit and the switch within a heterogeneous integrated circuit process.

27 . The method of claim 20 , further comprising configuring the DAC circuit to generate a signal at the output stage, the signal comprising a peak current in the range of 90 milliamps to 200 milliamps and a frequency greater than 40 Gigahertz.

Assignees

• Bae Sys Inf & Elect Sys Integ

Inventors

• Cali Joseph D
• Kushner Lawrence J
• Turner Steven E

Classifications

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D84/08

  using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies · CPC title

• H10D84/05

  using Group III-V technology · CPC title

• H10D84/01

  Manufacture or treatment · CPC title

• H10D84/40

  characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs · CPC title