INTEGRATED CIRCUITS WITH VERTICAL JUNCTIONS BETWEEN nFETS AND pFETS, AND METHODS OF MANUFACTURING THE SAME
US-2015357433-A1 · Dec 10, 2015 · US
Replacement metal gate including dielectric gate material
US2016172467A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016172467-A1 |
| Application number | US-201615062465-A |
| Country | US |
| Kind code | A1 |
| Filing date | Mar 7, 2016 |
| Priority date | Jan 30, 2014 |
| Publication date | Jun 16, 2016 |
| Grant date | — |
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- Title
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Abstract
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A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.
First claim
Opening claim text (preview).
What is claimed is: 1 . A method of fabricating a semiconductor device, the method comprising: forming at least one semiconductor fin on a semiconductor substrate; forming an etch stop layer on an upper surface of the at least one semiconductor fin; forming a plurality of gate formation layers on the etch stop layer and the substrate, the plurality of gate formation layers including a dummy gate layer formed from a dielectric material; patterning the plurality of gate form…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US2016172467A1 cover?
- A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy …
- Who is the assignee on this patent?
- IBM, Globalfoundries Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D64/017. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Jun 16 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).