Information processing device

Patent metadata

Field	Value
Publication number	US-2016170873-A1
Application number	US-201314905702-A
Country	US
Kind code	A1
Filing date	Jul 18, 2013
Priority date	Jul 18, 2013
Publication date	Jun 16, 2016
Grant date	—

Abstract

An information processing device includes a host and a memory subsystem. The host issues a write command or an erase command with tag information corresponding to data to the memory subsystem and includes an information processing circuit for processing the data. The memory subsystem includes a first memory, a second memory, and a memory subsystem control circuit. The first memory stores management information for managing the second memory. The second memory has a larger size of a data erase unit than a size of a data write unit and stores the data. The memory subsystem control circuit writes data on the same tag information in the same management unit and writes data on the different tag information in the different management unit, based on the management information in which n times of the data erase unit (“n” is a natural number) is a management unit.

First claim

1 . An information processing device, comprising a host and a memory subsystem, wherein
the host issues a write command or an erase command with tag information corresponding to data to the memory subsystem and comprises an information processing circuit configured to process the data, the memory subsystem comprises: a first memory storing management information for managing a second memory; the second memory having a larger size of a data erase unit than a size of a data write unit and configured to store the data; and a memory subsystem control circuit configured to write data on the same tag information in the same management unit and write data on the different tag information in the different management unit, based on the management information in which n times of the data erase unit (“n” is a natural number) is a management unit.

2 . The information processing device according to claim 1 , wherein the host comprises the information processing circuit configured to issue a read command with the tag information to the memory subsystem, and the memory subsystem comprises the memory subsystem control circuit configured to read data corresponding to the same tag information from the second memory and transfers the data to the host.

3 . The information processing device according to claim 1 , wherein the memory subsystem comprises the memory subsystem control circuit configured to erase the data corresponding to the same tag information from the second memory.

4 . The information processing device according to claim 1 , wherein the tag information includes information for identifying a group of a data processing unit of the host, information for identifying a super step which is a data processing step of the host, and a data type identifier configured to identify a type of the data processed by the host.

5 . The information processing device according to claim 1 , wherein the management information includes an association between an address in the second memory of the data and the tag information corresponding to the data, and the management information is stored in a table.

6 . The information processing device according to claim 1 , wherein the management information includes an association between the tag information and the management unit in which data corresponding to the tag information is written, and the management information is stored in a table.

7 . The information processing device according to claim 1 , wherein
the memory subsystem comprises: the first memory accessible at a higher speed than a speed of the second memory; and the second memory which is a nonvolatile memory.

8 . The information processing device according to claim 1 , wherein
the memory subsystem comprises: the first memory configured to store management information for managing a block of the second memory; the second memory configured to include a plurality of the blocks of a data erase unit and include a plurality of pages of a write unit in the block; and the memory subsystem control circuit configured to specify the block by referring to the management information and specify the page by calculation.

9 . An information processing device, comprising a host and a memory subsystem, wherein
the host issues a write command or an erase command to the memory subsystem, sets n times (“n” is a natural number) of a data erase unit of a memory in the memory subsystem to a management unit, associate between tag information and the management unit by management information, and comprises an information processing circuit configured to process the data, and the memory subsystem comprises: the memory having a larger size of the data erase unit than a size of a data write unit and configured to store the data; and a memory subsystem control circuit configured to, by the write command from the host, write data on the same tag information in the same management unit and write data on the different tag information in the different management unit.

10 . The information processing device according to claim 9 , wherein the host comprises the information processing circuit configured to issue a read command to the memory subsystem, and the memory subsystem comprises the memory subsystem control circuit configured to read data corresponding to the same tag information from the memory and forward the data to the host.

11 . The information processing device according to claim 9 , wherein the memory subsystem comprises the memory subsystem control circuit configured to erase the data corresponding to the same tag information from the memory.

12 . The information processing device according to claim 9 , wherein the tag information includes information for identifying a group which is a data processing unit of the host, information for identifying a super step which is a data processing step of the host, and a data type identifier configured to identify a type of data processed by the host.

13 . The information processing device according to claim 9 , wherein
the memory subsystem comprises: a first memory accessible at a higher speed than a speed of the memory; and the memory which is a nonvolatile memory.

14 . The information processing device according to claim 9 , wherein
the host specifies a block of the memory by referring to the management information, and comprises an information processing circuit configured to specify a page of the memory by calculation, and the memory subsystem comprises the memory including a plurality of the blocks which is a data erase unit and including, in the blocks, a plurality of the pages which is a write unit.

Assignees

• Hitachi Ltd

Inventors

• Uchigaito Hiroshi
• Miura Seiji
• Nito Takumi

Classifications

• G06F3/0652

  Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket · CPC title

• G06F12/0253 Primary

  Garbage collection, i.e. reclamation of unreferenced memory · CPC title

• G06F2212/1044

  Space efficiency improvement · CPC title

• G06F3/0608

  Saving storage space on storage systems · CPC title

• G06F2212/7205

  Cleaning, compaction, garbage collection, erase control · CPC title