Multiple-thread processing methods and apparatuses

Patent metadata

Field	Value
Publication number	US-2016170799-A1
Application number	US-201514816265-A
Country	US
Kind code	A1
Filing date	Aug 3, 2015
Priority date	Dec 12, 2014
Publication date	Jun 16, 2016
Grant date	—

Abstract

Multiple-thread processing apparatuses and methods are provided. The multiple-thread processing method may include searching for loops in a plurality of threads, calculating a number of repetitions of each of found loops in respective threads among the plurality of threads, determining one or more threads based on the calculated number of repetitions of each of the found loops, dividing at least one of the one or more determined threads into child threads, and processing the child threads separately from one another in the plurality of threads.

First claim

What is claimed is:

1 . A multiple-thread processing method comprising:
searching for loops in a plurality of threads; calculating a number of repetitions of each of found loops in respective threads among the plurality of threads; determining one or more threads among the plurality of threads based on the calculated number of repetitions of each of the found loops; dividing at least one of the one or more determined threads into child threads; and processing the child threads separately from one another in the plurality of threads.

2 . The multiple-thread processing method of claim 1 , further comprising processing the plurality of threads and performing reduction on the processed plurality of threads.

3 . The multiple-thread processing method of claim 1 , wherein the determining of the one or more threads comprises:
determining rankings of the respective threads among the plurality of threads in descending order of the calculated number of repetitions of each of the found loops; and determining the one or more threads based on the determined rankings of the respective threads among the plurality of threads.

4 . The multiple-thread processing method of claim 3 , wherein the determining of the one or more threads comprises determining a top-ranked thread.

5 . The multiple-thread processing method of claim 3 , wherein the determining of the one or more threads comprises determining a top-ranked thread and a second-ranked thread.

6 . The multiple-thread processing method of claim 1 , wherein the determining of the one or more threads comprises determining whether parallel reduction in the loops of the determined one or more threads is possible.

7 . The multiple-thread processing method of claim 1 , wherein the dividing comprises processing threads, among the plurality of threads, other than the one or more determined threads and dividing the one or more determined threads into child threads of each thread of the plurality of threads.

8 . The multiple-thread processing method of claim 1 , wherein the dividing comprises:
processing some threads among the plurality of threads; and dividing the one or more determined threads into child threads of the processed threads among the plurality of threads.

9 . The multiple-thread processing method of claim 2 , further comprising outputting a reduction result.

10 . A computer program stored in a medium, the computer program being combined with hardware to process the method of claim 1 .

11 . A multiple-thread processing apparatus comprising:
a search processor configured to search for loops in a plurality of threads; a calculator configured to calculate a number of repetitions of each of found loops in respective threads among the plurality of threads; a thread determiner configured to determine one or more threads among the plurality of threads based on the calculated number of repetitions of each of the found loops; a divider configured to divide at least one of the one or more determined threads into child threads; and a thread processor configured to process the child threads separately from one another in the plurality of threads.

12 . The multiple-thread processing apparatus of claim 11 , wherein the thread processor is further configured to process the plurality of threads, and the multiple-thread processing apparatus further comprises a thread reducer configured to perform reduction on the processed plurality of threads.

13 . The multiple-thread processing apparatus of claim 11 , wherein the thread determiner is configured to determine rankings of the respective threads among the plurality of threads in descending order of the calculated number of repetitions of each of the found loops and determine the one or more threads based on the determined rankings of the respective threads among the plurality of threads.

14 . The multiple-thread processing apparatus of claim 13 , wherein the thread determiner is configured to determine a top-ranked thread among the plurality of threads.

15 . The multiple-thread processing apparatus of claim 14 , wherein the thread determiner is configured to determine a top-ranked thread and a second-ranked thread among the plurality of threads.

16 . The multiple-thread processing apparatus of claim 11 , wherein the thread determiner is configured to determine whether parallel reduction in the loops of the one or more determined threads is possible.

17 . The multiple-thread processing apparatus of claim 11 , wherein the divider is configured to process threads, among the plurality of threads, other than the one or more determined threads and divide the one or more determined threads into child threads of each thread of the plurality of threads.

18 . The multiple-thread processing apparatus of claim 11 , wherein the divider is configured to process some threads among the plurality of threads, and divide the one or more determined threads into child threads of the processed threads among the plurality of threads.

19 . The multiple-thread processing apparatus of claim 12 , further comprising an output configured to output a reduction result.

20 . A multiple-thread processing apparatus comprising:
at least one processor configured to
determine a thread among a plurality of threads based on a calculated number of repetitions of a loop in respective threads among the plurality of threads,
divide the determined thread into child threads respectively allocated to selected threads among the plurality of threads, and
process the child threads respectively in the selected threads.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeong Minkyu
• Park Haewoo
• Son Minyoung
• Jang Choonki
• Choi Yoonseo
• Yoo Donghoon

Classifications

• G06F9/4881 Primary

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F9/466

  Transaction processing · CPC title

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F8/41

  Compilation · CPC title

• G06F8/4441

  Reducing the execution time required by the program code · CPC title