Signal processing circuit for mitigating pulling effect and associated method

Patent metadata

Field	Value
Publication number	US-2016164464-A1
Application number	US-201514738941-A
Country	US
Kind code	A1
Filing date	Jun 15, 2015
Priority date	Dec 9, 2014
Publication date	Jun 9, 2016
Grant date	—

Abstract

A signal processing circuit has a first mixer, a first amplifier, and a pulling effect mitigation circuit. The first mixer mixes a first input signal and a first oscillation signal to generate a first output signal, wherein the first oscillation signal is generated by dividing a frequency of a reference clock with a frequency dividing factor. The first amplifier amplifies the first output signal, and generates an amplified output signal at an output terminal of the first amplifier. The pulling effect mitigation circuit is coupled to the output terminal of the first amplifier, and generates a compensation signal to the output terminal for reducing at least an N th harmonic of the amplified output signal, wherein a value of N is equal to the frequency dividing factor.

First claim

What is claimed is:

1 . A signal processing circuit, comprising:
a first mixer, arranged to mix a first input signal and a first oscillation signal to generate a first output signal, wherein the first oscillation signal is generated by dividing a frequency of a reference clock with a frequency dividing factor; a first amplifier, coupled to the first mixer, the first amplifier arranged to amplify the first output signal and generate an amplified output signal at an output terminal of the first amplifier; and a pulling effect mitigation circuit, coupled to the output terminal of the first amplifier, the pulling effect mitigation circuit arranged to generate a compensation signal to the output terminal for reducing at least an N th harmonic of the amplified output signal; wherein a value of N is equal to the frequency dividing factor.

2 . The signal processing circuit of claim 1 , wherein the pulling effect mitigation circuit comprises:
a second mixer, arranged to mix a second input signal and a second oscillation signal to generate a second output signal, wherein a frequency of the first oscillation signal is equal to a frequency of the second oscillation signal; and a compensating unit, coupled to the second mixer, the compensating unit arranged to generate the compensation signal according to the second output signal, wherein the compensating unit makes a phase of an N th harmonic of the compensation signal have a 180-degree difference with a phase of the amplified output signal.

3 . The signal processing circuit of claim 2 , wherein the second output signal is phase-shifted from the first output signal.

4 . The signal processing circuit of claim 3 , wherein the second input signal is phase-shifted from the first input signal.

5 . The signal processing circuit of claim 4 , wherein the second input signal is phase-shifted 90-degrees from the first input signal.

6 . The signal processing circuit of claim 3 , wherein the second oscillation signal is phase-shifted from the first oscillation signal.

7 . The signal processing circuit of claim 6 , wherein the second oscillation signal is phase-shifted 90-degrees from the first oscillation signal.

8 . The signal processing circuit of claim 3 , wherein the second output signal is phase-shifted 90-degrees from the first output signal.

9 . The signal processing circuit of claim 8 , wherein the compensating unit is a squarer.

10 . The signal processing circuit of claim 8 , wherein the compensating unit is a second amplifier.

11 . A signal processing method, comprising:
mixing a first input signal and a first oscillation signal to generate a first output signal, wherein the first oscillation signal is generated by dividing a frequency of a reference clock with a frequency dividing factor; amplifying the first output signal to generate a first amplified output signal; generating a compensation signal; and combining the first amplified output signal and the compensation signal for reducing at least an N th harmonic of the first amplified output signal; wherein a value of N is equal to the frequency dividing factor.

12 . The signal processing method of claim 11 , wherein generating the compensation signal comprises:
mixing a second input signal and a second oscillation signal to generate a second output signal, wherein a frequency of the first oscillation signal is equal to a frequency of the second oscillation signal; and generating the compensation signal according to the second output signal, wherein a phase of an N th harmonic of the compensation signal has a 180-degree difference with a phase of the first input signal.

13 . The signal processing method of claim 12 , wherein the second output signal is phase-shifted from the first output signal.

14 . The signal processing method of claim 13 , wherein the second input signal is phase-shifted from the first input signal.

15 . The signal processing method of claim 14 , wherein the second input signal is phase-shifted 90-degrees from the first input signal.

16 . The signal processing method of claim 13 , wherein the second oscillation signal is phase-shifted from the first oscillation signal.

17 . The signal processing method of claim 16 , wherein the second oscillation signal is phase-shifted 90-degrees from the first oscillation signal.

18 . The signal processing method of claim 13 , wherein the second output signal is phase-shifted 90-degrees from the first output signal.

19 . The signal processing method of claim 18 , wherein generating the compensation signal comprises:
squaring the second output signal to generate the compensation signal.

20 . The signal processing method of claim 18 , wherein generating the compensation signal comprises:
amplifying the second output signal to generate the compensation signal.

Assignees

• Mediatek Inc

Inventors

• Sun Chih-Hao

Classifications

• H03D2200/009

  Reduction of local oscillator or RF leakage · CPC title

• H03D7/00

  Transference of modulation from one carrier to another, e.g. frequency-changing (H03D9/00, H03D11/00 take precedence; dielectric amplifiers, magnetic amplifiers, parametric amplifiers used as a frequency-changers H03F) · CPC title

• H03K5/00006 Primary

  Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68) · CPC title

• H03D7/14 Primary

  Balanced arrangements · CPC title