Forming led structures on silicon fins

Patent metadata

Field	Value
Publication number	US-2016163918-A1
Application number	US-201314906542-A
Country	US
Kind code	A1
Filing date	Sep 27, 2013
Priority date	Sep 27, 2013
Publication date	Jun 9, 2016
Grant date	—

Abstract

Methods of forming III-V LED structures on silicon fin templates are described. Those methods and structures may include forming an n-doped III-V layer on a silicon ( 111 ) plane of a silicon fin, forming a quantum well layer on the n-doped III-V layer, forming a p-doped III-V layer on the quantum well layer, and then forming an ohmic contact layer on the p-doped III-V layer.

First claim

What is claimed is:

1 . A method of forming a light emitting diode (LED) structure comprising:
forming an n-doped III-V layer on a silicon ( 111 ) plane of a silicon fin structure; forming a quantum well layer on the p-doped III-V layer; forming a p-doped III-V layer on the quantum well layer; and forming an ohmic contact layer on the p-doped III-V layer.

2 . The method of claim 1 further comprising wherein the n doped III-V layer comprises one of gallium nitride and indium gallium nitride.

3 . The method of claim 1 further comprising wherein the n-doped III-V layer is epitaxially grown, and comprises a thickness of between about 40 nm and about 150 nm.

4 . The method of claim 1 further comprising wherein the n-doped III-V layer is substantially defect free.

5 . The method of claim 1 further comprising wherein the quantum well layer comprises a multi-quantum well structure that comprises at least one of an indium gallium nitride layer, an aluminum gallium nitride layer and a gallium nitride layer.

6 . The method of claim 5 further comprising wherein the indium gallium nitride layer comprises about 5 to about 30 percent indium by weight, and wherein a thickness of the indium gallium nitride layer comprises between about 5 to about 10 nm.

7 . The method of claim 5 further comprising wherein the gallium nitride layer comprises a thickness of between about 5 to about 10 nm.

8 . The method of claim 5 wherein the multi-quantum well may comprise at least about 5 layers, wherein each layer comprises a gallium nitride layer disposed on an indium gallium nitride layer.

9 . The method of claim 1 further comprising wherein the p-doped III-V layer comprises a gallium nitride layer, and comprises a thickness between about 40 nm and about 50 nm.

10 . The method of claim 9 further comprising wherein forming a plurality of LED's on in an array on a ( 100 ) substrate.

11 . The method of claim 1 further comprising wherein the silicon fin is disposed on an n-doped silicon ( 100 ) substrate, wherein the substrate comprises a portion of a system on a chip.

12 . The method of claim 1 further comprising wherein the ohmic contact comprises an indium tin oxide.

13 . The method of claim 11 further comprising forming an n-type metal on a backside of the substrate.

14 . The method of claim 1 further comprising wherein the quantum well layer comprises a top portion and two side portions, wherein the side portions are grown on the silicon ( 111 ) planes of the silicon nanofin.

15 . The method of claim 14 further comprising wherein the quantum well layer grown the side portions are grown on a c-plane, and the quantum well layer grown on the top portion are grown on the m-plane.

16 . The method of claim 1 further comprising wherein a top portion of the silicon fin is covered by a dielectric material, wherein the quantum well layer grown on the side portions comprise a c-plane, and the quantum well layer grown on the top portion comprises an m plane.

17 . A method of forming an LED structure comprising:
forming an p-doped III-V layer on a silicon ( 111 ) plane of a silicon fin, wherein the silicon fin is disposed on a p+ doped silicon ( 100 ) substrate; forming a quantum well structure on the III-V layer; forming an n doped III-V layer on the quantum well structure; forming an n type ohmic contact layer on the n-doped III-V layer; and forming a p contact metal on a back side of the substrate.

18 . The method of claim 17 further comprising wherein the n doped III-V layer and the p doped III-V layer comprise at least one of gallium nitride and indium gallium nitride are epitaxially grown.

19 . The method of claim 17 further comprising wherein the n type ohmic contact comprises at least one of a nickel material, a gold material, and alloys thereof.

20 . An LED structure comprising:
an n-doped III-V layer disposed on a silicon ( 111 ) plane of a silicon fin; a quantum well layer disposed on the n-doped III-V layer; a p-doped III-V layer disposed on the quantum well layer; and an ohmic contact layer disposed on the p-doped III-V layer.

21 . The structure of claim 20 further comprising wherein the n-doped III-V layer and the p-doped III-V layer comprise one of a gallium nitride and indium gallium nitride.

22 . The structure of claim 20 further comprising wherein the n-doped III-V layer is epitaxially grown, and comprises a thickness of between about 40 nm and about 150 nm.

23 . The structure of claim 20 further comprising wherein the n-doped III-V layer is substantially defect free.

24 . The structure of claim 20 further comprising wherein the quantum well layer comprises a multi-quantum well structure that comprises at least one of an indium gallium nitride layer, an aluminum gallium nitride layer and a gallium nitride layer.

25 . The structure of claim 24 further comprising wherein the indium gallium nitride layer comprises about 5 to about 30 percent indium by weight, and wherein a thickness of the indium gallium nitride layer comprises between about 5 to about 10 nm, and wherein the gallium nitride layer comprises a thickness of between about 5 to about 10 nm.

26 . The structure of claim 20 further comprising wherein the silicon fin is disposed on an n-doped silicon ( 100 ) substrate, wherein the substrate comprises a portion of a system on a chip.

27 . The structure of claim 20 further comprising wherein the ohmic contact layer comprises an indium tin oxide.

28 . The structure of claim 20 further comprising wherein the quantum well layer comprises a top portion and two side portions, wherein the side portions comprises a c-plane, and the top portion comprises an m plane.

29 . The method of claim 20 further comprising wherein the LED structure comprises a portion of a blue/green LED device.

30 . The structure of claim 20 further comprising a system comprising:
a bus communicatively coupled to the LED structure; and
an eDRAM communicatively coupled to the bus.

Assignees

• Intel Corp

Inventors

• Dasgupta Sansaptak
• Then Han Wui
• Chau Robert S
• Radosavljevic Marko
• Chu-Kung Benjamin
• Gardner Sanaz

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10P14/3216

  Nitrides · CPC title

• H10P14/2926

  Crystal orientations · CPC title

• H10P14/2925

  Surface structures · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title