Integrated circuit package with power plates

Patent metadata

Field	Value
Publication number	US-2016163671-A1
Application number	US-201414559893-A
Country	US
Kind code	A1
Filing date	Dec 3, 2014
Priority date	Dec 3, 2014
Publication date	Jun 9, 2016
Grant date	—

Abstract

A surface-mounted integrated circuit package containing a semiconductor die has at least two conductive plates on its lower surface for contacting power and ground areas of a printed circuit board (PCB). The conductive plates are electrically connected to metal studs encapsulated within the package and which link the plates to the power and ground grids of the semiconductor die. Power and ground can thus be provided to the package with conductive patterns on the PCB that match with the plates. The resistance of the plates is low and hence the IR drop across the die is low. By supplying power directly to the package via the plates, the peripheral package pins that would otherwise have been allocated for power (and ground) are now freed up for signal assignment.

First claim

1 . An integrated circuit package for mounting on a printed circuit board (PCB), comprising:
a lead frame having a die flag and a plurality of leads that surround the die flag, wherein each lead has a proximal end co-planar with the die flag and an opposite distal end; a semiconductor die having an active side that has a power terminal, a ground terminal and a plurality of signal terminals located thereon, and an opposite back side mounted on the die flag of the lead frame; a first connector arrangement connected to the power terminal; a second connector arrangement connected to the ground terminal; a first conductive plate connected to the first connector arrangement, wherein the first conductive plate is located at a first external face of the package; a second conductive plate connected to the second connector arrangement, wherein the second conductive plate is located at a second external face of the package, wherein the first conductive plate is for connection to a power area of the PCB and the second conductive plate is for connection to a ground area of the PCB; and a molding compound that encapsulates the die and the first and second connector arrangements, wherein the distal end of each lead protrudes from the molding compound and is bent towards the active side of the semiconductor die for mounting the distal end of each lead to the PCB, wherein the first and second conductive plates are separated and electrically isolated from each other by the molding compound.

2 . The integrated circuit package of claim 1 , wherein each of the first and second connector arrangements comprises at least one metal stud.

3 . The integrated circuit package of claim 1 , wherein each of the first and second connector arrangements comprises at least one solder ball.

4 . The integrated circuit package of claim 1 , wherein the first and second conductive plates are copper.

5 . The integrated circuit package of claim 1 , wherein the first and second conductive plates are soldered to the first and second connector arrangements respectively.

6 . (canceled)

7 . The integrated circuit package of claim 1 , wherein the die signal terminals are electrically connected to respective ones of the leads with bond wires.

8 . (canceled)

9 . A method for assembling an integrated circuit package for mounting on a printed circuit board (PCB), comprising the steps of:
forming a power terminal and a ground terminal on an active side of a semiconductor die; attaching a first connector arrangement to the power terminal; attaching a second connector arrangement to the ground terminal; attaching a first conductive plate, for contacting a power area of the PCB, to the first connector arrangement; attaching a second conductive plate, for contacting a ground area of the PCB, to the second connector arrangement; providing a lead frame having a die flag and a plurality of leads that surround the die flag, wherein each lead has a proximal end co-planar with the die flag and an opposite distal end; attaching a back side of the semiconductor die to the die flag; encapsulating the semiconductor die and the first and second connector arrangements in a molding compound, wherein the first and second conductive plates are separated and electrically isolated from each other by the molding compound, and are exposed for contacting respective power and ground areas of the PCB, and wherein the distal ends of the leads protrude from the molding compound; and bending the distal ends of the leads outside of the molding compound towards the active side of the semiconductor die for mounting the distal ends of the leads to the PCB.

10 . The method of claim 9 , wherein the first and second connector arrangements are electrically connected to the power and ground terminals respectively using bond wires.

11 . (canceled)

12 . The method of claim 9 , further comprising attaching the first and second conductive plates to the first and second connector arrangements respectively using a soldering process.

13 . (canceled)

14 . The method of claim 9 , further comprising encapsulating the semiconductor die after attaching the first and second conductive plates to the first and second connector arrangements respectively.

15 . The method of claim 9 , further comprising attaching the first and second conductive plates to the first and second connector arrangements respectively after encapsulating the semiconductor die.

16 . The method of claim 15 , further comprising forming holes in the molding compound through to the power and ground terminals, and plugging the formed holes with solder balls.

17 . An integrated circuit package, comprising:
a lead frame including a die flag and a plurality of leads that surround the die flag, wherein each lead has a proximal end co-planar with the die flag and an opposite distal end; a semiconductor die having a back side attached to the die flag and a front, active side having a power terminal, a ground terminal and a plurality of signal terminals, wherein the leads are bent towards the active side of the semiconductor die for mounting the distal ends of the leads to a PCB; a first connector arrangement connected to the power terminal; a second connector arrangement connected to the ground terminal; a first conductive plate connected to the first connector arrangement, wherein the first conductive plate is located at a first external face of the package; a second conductive plate connected to the second connector arrangement, wherein the second conductive plate is located at a second external face of the package; bond wires electrically connecting the die signal terminals to respective ones of the leads; and a mold compound that covers the die, bond wires, and first and second connector arrangements, wherein the first and second conductive plates are separated and electrically isolated from each other by the molding compound.

18 . The integrated circuit package of claim 17 , wherein the first and second connector arrangements comprise conductive metal studs.

19 . The integrated circuit package of claim 17 , wherein the first and second external faces are the same face.

20 . The integrated circuit package of claim 19 , wherein the first and second conductive plates are flush with the external face.

Assignees

• Kumar Shailesh
• Bhooshan Rishi
• Foong Chee Seng
• Garg Vikas
• Kalandar Navas Khan Oratti
• Verma Chetan
• Freescale Semiconductor Inc

Inventors

• Kumar Shailesh
• Bhooshan Rishi
• Foong Chee Seng
• Garg Vikas
• Kalandar Navas Khan Oratti
• Verma Chetan

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/726

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9413

  on encapsulations · CPC title